Qualcomm Incorporated

Ganesh Kiran

Lei Sun

Seyed Arash Mirhaj

Dinesh Jagannath Alladi

Liang Dai

Omid Rajaee

Kentaro Yamamoto

Aram Akhavan

Robert J Littrell

Louis Dominic Oliveira

Elias Dagher

Bengt Stefan Gustavsson

Tomer Saraf

Changsok Han

William Wei-Ting Kuo

Mechanisms for detecting a voltage level on a data communication interface between a slave device and a host device are disclosed. Based on the detected voltage level, the slave device may respond to the host device on the data communication interface at the detected voltage level. The slave device may include a circuit configured to toggle between a first voltage level and a second voltage level to provide one of the first voltage level or the second voltage level corresponding to the detected voltage level on the data communication interface.

Voltage detector in data communication interface

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

Gain stabilization

Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

Output common-mode control for dynamic amplifiers

A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.

Bootstrapped switch circuit with improved speed

Methods and apparatus for digitally controlling a common-mode voltage of a comparator. An example comparator circuit generally includes a first comparator and a sensing circuit configured to digitally track a common-mode voltage of the first comparator. The comparator circuit may further include a first capacitive array having a common terminal coupled to a first input of the first comparator and selectively coupled to an input of the sensing circuit. The comparator circuit may further include a second capacitive array having a common terminal coupled to a second input of the first comparator and selectively coupled to the input of the sensing circuit.

Digitally assisted control over comparator input common mode

Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

Segmented successive approximation register (SAR) analog-to-digital converter (ADC) with reduced conversion time

Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

Growing community of inventors

San Diego, CA, United States of America

Ganesh Kiran