Samsung Electronics Co., Ltd.

Purdue Research Foundation

Ganesh Hegde

Mark Stephen Rodder

Jorge A Kittl

Harsono S Simka

Rwik Sengupta

Robert Christopher Bowen

Tillmann Christoph Kubis

Chris Bowen

Gerhard Klimeck

Mykhailo Povolotskyi

Borna Josip Obradovic

Joon Goo Hong

A method for obtaining learned self-consistent electron density and/or derived physical quantities includes: conducting non-self-consistent (NSC) calculation to generate a first NSC dataset Xfrom a first plurality of configurations of atoms; conducting self-consistent (SC) calculation to generate a first SC dataset Yfrom the first plurality of configurations of atoms; mapping the first NSC dataset Xto the first SC dataset Yutilizing machine learning algorithm to generate a mapping function F; and generating a learned self-consistent data Yfrom a new NSC data Xutilizing the mapping function F.

Electronic and atomic structure computation utilizing machine learning

A method and a system for material design utilizing machine learning are provided, where the underlying joint distribution p(S,P) of structure (S)-property (P) relationships is explicitly learned simultaneously and is utilized to directly generate samples (S,P) in a single step utilizing generative techniques, without any additional processing steps. The subspace of structures that meet or exceed the target for property P is then identified utilizing conditional generation of the distribution (e.g., p(P)), or through randomly generating a large number of samples (S,P) and filtering (e.g., selecting) those that meet target property criteria.

Generative structure-property inverse computational co-design of materials

A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

Interconnects having long grains and methods of manufacturing the same

A method for characterizing a material for use in a semiconductor device and the semiconductor device using the material are described. The material has a unit cell and a crystal structure. The method includes determining a figure of merit (FOM) for the material using only forward conducting modes for the unit cell. The FOM is a resistivity multiplied by a mean free path. The FOM may be used to determine a suitability of the material for use in the semiconductor device.

Method of screening materials using forward conducting modes

A method of forming an interconnect for an integrated circuit includes: identifying an interconnect barrier material, identifying a plurality of potential dopant elements, creating an ensemble of potential barrier structures including the interconnect barrier material doped at a plurality of doping positions and a plurality of doping amounts for each of the plurality of potential dopant elements, calculating a density of states for each of the barrier structures of the ensemble, selecting a dopant element and a doping amount based on the density of states, and depositing a barrier layer including an alloy, the alloy including the interconnect barrier material and the selected dopant element at the selected doping amount.

Low resistivity interconnects with doped barrier layer for integrated circuits

A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

Method and system for providing a reverse engineering resistant hardware embedded security module

A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an Inter Layer Dielectric (ILD). The ILD comprises a dielectric matrix having a first density. A dopant material layer is formed on the trench structure in which the dopant material layer comprises atoms of at least one of a rare-earth element. The ILD and the trench structure are annealed to form a dielectric matrix comprising a second density in one or more regions of the ILD on which the dopant material layer was formed that is greater than the first density. After annealing, the dielectric matrix comprising the second density includes increased bond lengths of oxygen-silicon bonds and/or oxygen-semiconductor bonds, increased bond angles of oxygen-silicon bonds and/or oxygen-semiconductor material bonds, and pores in the dielectric matrix are sealed compared to the dielectric matrix comprising the first density.

Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same

A method provides a source-drain stressor for a semiconductor device including source and drain regions. Recesses are formed in the source and drain regions. An insulating layer covers the source and drain regions. The recesses extend through the insulating layer above the source and drain regions. An intimate mixture layer of materials A and B is provided. Portions of the intimate mixture layer are in the recesses. The portions of the intimate mixture layer have a height and a width. The height divided by the width is greater than three. A top surface of the portions of the intimate mixture layer in the recesses is free. The intimate mixture layer is reacted to form a reacted intimate mixture layer including a compound AB. The compound ABoccupies less volume than a corresponding portion of the intimate mixture layer.

Method of providing reacted metal source-drain stressors for tensile channel stress

A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

Method and system for providing a reverse-engineering resistant hardware embedded security module

A method for modeling a material at least partially-defined by atomic information includes, for each of a plurality of configurations of the material, determining energy moments for a density of states of the respective configuration of the material, and generating a tight binding Hamiltonian matrix for the respective configuration of the material. The method further includes, for each of the plurality of configurations of the material, forming a tight binding model of the configuration of the material by resolving a linking of (i) the energy moments for the density of states of the material to (ii) the tight binding Hamiltonian matrix for the material. Still further the method includes, based on the tight binding models for each of the configurations of the material, forming an environmentally-adapted tight binding model.

Physical modeling of electronic devices/systems

Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.

Methods of forming semiconductor devices including conductive contacts on source/drains

A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.

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Austin, TX, United States of America

Ganesh Hegde