International Business Machines Corporation

Advanced Micro Devices Corporation

Lenovo (singapore) Pte. Ltd.

Ganesh Balakrishnan

Vydhyanathan Kalyanasundharam

Amit P Apte

Kevin Michael Lepak

Anil Krishna

Srinivasan Ramani

Brian Michael Rogers

Ken Van Vu

Jeffrey A Stuecheli

Bartholomew Blaner

Ravindra Nath Bhargava

Mohammad Peyravian

Jorge Rolando Rodriguez

Ann M Ling

Eric Christopher Morton

John J Reilly

Gordon Bernard Bell

Clark Debs Jeffries

Bulent Abali

Peter Anthony Sandon

Ravinder Kumar Sabhikhi

Chintan S Patel

Raj Kumar Singh

Elizabeth Morrow Cooper

Joe J Sargunaraj

Michael Steven Siegel

Alexander J Branover

Christopher Jude Brennan

Michael Raymond Trombley

Timothy Hume Heil

Everett Arthur Corl, Jr

Bejoy J Kochuparambil

Bryan P Broussard

Aparna Vallury

Rama Mohan Yedavalli

Matthew L Nickerson

Akshay Lahiry

Larry W Nicholson

Girish Balaiah Aswathaiya

Li Ou

Mvv Anil Krishna

Jitesh R Nair

John P Chalmers

A method includes, in a cache directory, storing a set of entries corresponding to one or more memory regions having a first region size when the cache directory is in a first configuration, and based on a workload sparsity metric, reconfiguring the cache directory to a second configuration. In the second configuration, each entry in the set of entries corresponds to a memory region having a second region size.

Dynamically altering tracking granularity in a region-based cache directory

The disclosed computer-implemented method includes interleaving a plurality of caches corresponding to a plurality of chiplets, identifying a source chiplet ID of a memory request of a new address for the interleaved caches, and storing, using an indexing scheme that incorporates the source chiplet ID, a shadow tag for a cache of the interleaved caches corresponding to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Shadow tag management for accelerator partitions

Adaptive system probe action to minimize input/output dirty data transfers is described. In one or more implementations, a system includes a processor, a memory configured to store data, and a cache configured to store a portion of the data stored in the memory for execution by the processor. The system also includes a cache coherence controller including a cache line history. The cache coherence controller is configured detect a direct memory access request from an input/output device. The direct memory access request is associated with an input/output operation involving the data. The cache coherence controller is further configured to identify a cache line associated with the direct memory access request, and, in response to the cache line history including a dirty data transfer record corresponding to the cache line, selectively send a probe to the cache based on a state of the cache line.

Adaptive system probe action to minimize input/output dirty data transfers

The disclosed computer-implemented method includes detecting a low utilization time period for memory traffic between a cache and memory, selecting from the cache, in response to detecting the low utilization time period, a dirty cache entry based on one or more factors, and writing the dirty cache entry back to the memory during the low utilization time period. Various other methods, systems, and computer-readable media are also disclosed.

Dynamically controlled cache rinsing

A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

Coherent block read fulfillment

The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.

Tiered memory caching

Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

Region based split-directory scheme to adapt to large cache sizes

A data processing system includes a plurality of coherent masters, a plurality of coherent slaves, and a coherent data fabric. The coherent data fabric has upstream ports coupled to the plurality of coherent masters and downstream ports coupled to the plurality of coherent slaves for selectively routing accesses therebetween. The coherent data fabric includes a probe filter and a directory cleaner. The probe filter is associated with at least one of the downstream ports and has a plurality of entries that store information about each entry. The directory cleaner periodically scans the probe filter and selectively removes a first entry from the probe filter after the first entry is scanned.

Probe filter directory management

A method includes, in a cache directory, storing an entry associating a memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state.

Page rinsing scheme to keep a directory page in an exclusive state in a single complex

A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

Mechanism to efficiently rinse memory-side cache of dirty data

Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.

Region based directory scheme to adapt to large cache sizes

Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.

Multi-level cache coherency protocol for cache line evictions

Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.

Home agent based cache transfer acceleration scheme

Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.

Scalable region-based directory

Growing community of inventors

Apex, NC, United States of America

Ganesh Balakrishnan