Texas Instruments Corporation

Ganesan Thiagarajan

Udayan Dasgupta

Venugopal Gopinathan

Abhijit Anant Patki

David Patrick Magee

Tarkesh Pande

Madhulatha Bonu

Janakiraman S

Sthanunathan Ramakrishnan

Arup Polley

Terry Lee Sculley

Amit Premy

In described examples, a method for detecting voice activity includes: receiving a first input signal containing noise; sampling the first input signal to form noise samples; determining a first value corresponding to the noise samples; subsequently receiving a second input signal; sampling the second input signal to form second signal samples; determining a second value corresponding to the second signal samples; forming a ratio of the second value to the first value; comparing the ratio to a predetermined threshold value; and responsive to the comparing, indicating whether voice activity is detected in the second input signal.

Methods and apparatus for low cost voice activity detector

Methods and apparatus for magnetic sensors and integrated calibration. In an example arrangement, a system includes a magnetic sensor configured to output a signal corresponding to magnetic fields; a calibration trace disposed proximal to the magnetic sensor; a controlled current source coupled to the calibration trace and configured to output a current resulting in a magnetic field output from the calibration trace; and a comparator coupled to the output signal from the magnetic sensor and to an expected signal. In the example arrangement, the comparator outputs a signal indicating whether the output signal from the magnetic sensor corresponds to the expected signal. Methods are also disclosed.

Methods and apparatus for magnetic sensor with integrated calibration mechanism

A bandwidth estimator circuit for an analog to digital converter. The bandwidth estimator computes a bandwidth estimate of an analog signal and includes: an amplitude averaging block configured to determine an average change in amplitude of N samples, a delta time block configured to determine a minimum time difference; a peak voltage block configured to determine the maximum magnitude; a peak to root mean square block configured to determine a ratio of a peak voltage to the root mean square of the magnitude; a bandwidth estimator block configured to compute a product of a ratio of the average change in amplitude to the minimum time difference, multiplied by a ratio of the peak voltage to the root mean square, squared, to the peak voltage multiplied by a constant; and a parameter adjustment circuit configured to modify sampler parameters controlling an analog signal sampling rate. Methods are described.

Circuits and methods for bandwidth estimation optimization of analog to digital converters

A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time difference between the asynchronous samples surrounding the selected sample, and the five linear slopes of the line segments between the three points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.

Asynchronous to synchronous sampling using Akima algorithm

A snapout calculator, and wherein the snapout calculator determines where the reference levels for the various comparators shall be placed after each asynchronous sample is generated.

Asynchronous sampling using a dynamically adustable snapback range

A method, comprising: selecting two Two-Tuples before and two after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time differences between each of the asynchronous samples surrounding the selected sample, and the three linear slopes of the line segments between the two points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.

Asynchronous to synchronous sampling using modified akima algorithm

An apparatus, comprising: an analog to digital converter including: a clipping detector; and a post-processor, wherein the post processor generates synchronous values of clipped data based on non-clipped values of non-clipped data.

Extension of ADC dynamic range using post-processing logic

A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing.

Asynchronous sampling using dynamically configurable voltage polling levels

A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse asynchronous to synchronous conversion using the plurality of 2-tuples to generate a plurality of low precision synchronous outputs; generating a high precision synchronous output, z, using a plurality of asynchronous 2-tuples, low precision synchronous outputs after it, and its own high precision outputs from previous steps; calculating cand cby summing future low precision outputs and the past high precision outputs after they are weighted with the appropriate windowed sinc. values and then subtracted from appropriate asynchronous samples; calculating, the four quantities 's', 's', &#x201c;s&#x201d; and &#x201c;s&#x201d; based on particular values of the windowed sinc. function; and using c, c, s, s, sand s, the high precision synchronous output of interest, zis generated.

Asynchronous to synchronous sampling using an augmented least squares solver

A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

Asynchronous analog-to-digital converter having adapative reference control

A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.

Asynchronous analog-to-digital converter

An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

Asynchronous analog-to-digital converter having rate control

Selecting one of multiple antennas to receive signals in a wireless packet network. Correlation value and gain needed to boost the signal up to a desired power (or the signal strength of the received signal) are determined for each antenna by examining the non-payload portion (e.g., preamble) of the packet. The antenna with the best SNR is then chosen based on the rule given. In an embodiment, the correlation value is determined based on the Barker Sequence employed for each bit in the preamble. The selection may be performed for each data packet, thereby using the antenna receiving the signal most conducive to recovery of the data bits (including payload) in each data packet.

Selecting one of multiple antennas to receive signals in a wireless packet network

Testing of a mixed signal integrated circuit (IC) potentially in the form of a die using a tested/calibrated integrated circuit. In an embodiment, the mixed signal IC generates an analog signal from a symbol, and transmits the analog signal to the calibrated integrated circuit. The calibrated IC determines a valid symbol corresponding to the signal level (e.g., voltage) of the received analog signal, and determines a deviation of the signal level of the received analog signal from the voltage level corresponding to the valid symbol. The deviation is deemed to represent the degree of defect of the mixed signal IC based on the assumption that the calibrated IC operates accurately. The deviation is used to either discard or qualify/accept the mixed signal IC.

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Bengaluru, India

Ganesan Thiagarajan