Intel Corporation

Omics Data Automation, Inc.

Providence Health & Services

Datma, Inc.

Ganapati Srinivasa

Yen-Cheng Liu

Krishnakanth Venkata Sistla

Geeyarpuram N Santhanakrishnan

David A Koufaty

Eliezer Weissmann

Alon Naveh

Dheeraj R Subbareddy

Eugene Gorbatov

Michael Mishaeli

Scott D Hahn

P Keong Or

Hisham Shafi

Paolo L Narvaez

Mishali Naik

Paul Brett

Mark Rowland

Abirami Prabhakaran

Andrew J Herdrich

Inder M Sodhi

Russell Jerome Fenger

Theodros Yigzaw

Gaurav Khanna

Mohan J Kumar

Robert G Blankenship

Bahaa Fahim

Andrew D Henroid

Jose Andy Vargas

Julius Yuli Mandelblat

Zeev Sperber

Shlomo Raikin

Ehud Cohen

Jeffrey D Gilbert

Bret L Toll

Jason W Brandt

Ravishankar Iyer

Stephen Anthony Fischer

Vivek Garg

Dean A Mulla

Sridhar Muthrasanallur

Kenneth C Creta

Ashish V Choubal

Rinat Rappoport

Gopalan Ramanujam

Nagabhushan Chitlur

Oron Lenz

Glenn M Lewis

Nalini Ganapati

Christopher J Shannon

Jaclyn Smith

Hollis Wright

Calvin J Lin

Jeffrey A Larson

Arunachalam S Prakash

Sanjeev S Sahagirdar

Suresh Doraiswamy

Melvin Lathara

Brian Hill

Debendra Das Sharma

Efraim Rotem

Ronny Ronen

Christopher P Mozak

Boris Ginzburg

Guy M Therien

Robert J Safranek

Bryant E Bigbee

Lihu Rappoport

Anil Aggarwal

Larisa Novakovsky

Yuval Yosef

Avi Mendelson

Oded Lempel

Chen Koren

Michael F Cole

Donald L Pearson

George Cai

Mysore Sriram

Krishnakanth Sistia

Hemanth Kumar

Kevin Lee Matlock

Brian Donald Piening

Carlo B Bifulco

Russel J Fenger

Guarav Khanna

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

Methods and systems are provided for automatically classifying cells in a histological stained image. In an example, a method includes automatically classifying a plurality of cells in an image of a biological sample stained with a histological stain using a classification model, the classification model trained with a plurality of automatically-classified pseudo-stained images each generated from a respective immunofluorescent image.

System and method for automatic labeling of pathology images

Methods and systems are provided for a platform and language agnostic method for generating inter-and intra-data type aggregations of heterogeneous disparate data upon which various operations can be performed without altering the structure of the query or resulting distributed data set representation to account for which specific data sources are included in the query.

System and method for integrating data for precision medicine

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Optimizing power usage by factoring processor architectural events to PMU

Methods and systems are provided for a platform and language agnostic method for generating inter- and intra-data type aggregations of heterogenous disparate data upon which various operations can be performed without altering the structure of the query or resulting distributed data set representation to account for which specific data sources are included in the query.

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Migrating tasks between asymmetric computing elements of a multi-core processor

A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets

Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.

Ring protocol for low latency interconnect switch

An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

Apparatus and method for intelligently powering heterogeneous processor components

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Apparatus and method for heterogeneous processors mapping to virtual cores

Growing community of inventors

Portland, OR, United States of America

Ganapati Srinivasa