Telefonaktiebolaget Lm Ericsson (publ)

Gan Wen

Peng Liu

Qiang Wang

Jinsong Yang

Yahui Liu

Junfeng Jie

Guangfeng Liu

Hao Gao

Ge Hua Huang

Wenjia Li

Kaifeng Zhang

Tonghai Gao

Device and method are disclosed for downlink gain compensation at a radio unit. According to an embodiment, the device comprises a pre-distortion circuit, a digital gain adjuster, a gain determiner and a first gain controller. The pre-distortion circuit is configured to generate and apply a pre-distortion to an input signal. The digital gain adjuster is configured to apply an adjustable gain to an output signal from the pre-distortion circuit. The gain determiner is configured to determine a gain difference between a target downlink gain and current downlink gain. The first gain controller is configured to control the digital gain adjuster based on the gain difference. A radio unit comprising the device is also disclosed.

Device and method for downlink gain compensation as well as radio unit comprising the device

A dynamic configuration of crest factor reduction in a licensed assisted access radio system. A processing device comprises a detecting block, a clipping pulse generator, a first storage block, a selecting block, a full clipping block and a simplified clipping block. The detecting block performs a listen-before-talk (LBT) procedure on a plurality of carriers in parallel and generates a trigger signal in response to LBT success on one or more carriers. The clipping pulse generator generates, for the carrier(s) with LBT success, a clipping pulse within a time period from the receipt of the trigger signal to the start of user traffic transmission. The first storage block stores the clipping pulse for use by the full clipping block. The selecting block selects the full clipping block when there is user traffic on the carrier(s) and selects the simplified clipping block when there is no user traffic on the carrier(s).

Device and method for signal processing in licensed assisted access radio system

A method for communications is proposed. The method may comprise receiving, by a first network node, a report of clock quality of a second network node from a third network node. A clock of the first network node is selected as a master clock for synchronization in a first timing domain, a clock of the second network node is selected as a is selected as a master clock for synchronization in a second timing domain, and the third network node is attached to at least the first timing domain and the second timing domain. Based at least in part on the received report, it may be determined whether to synchronize the first timing domain to the second timing domain. In response to the determination of synchronizing the first timing domain to the second timing domain, the first network node can obtain timing information of the second network node from the third network node. The method may further comprise tuning the clock of the first network node to synchronize the first timing domain to the second timing domain, based at least in part on the timing information of the second network node.

Cross domain synchronization in a communication network

A method for adaptive signal processing is provided. In the method, a second vector is obtained by initializing a first vector without regularization of a cost function. The cost function is regularized with the first vector and the second vector as variables. The first vector is updated based on an input signal, according to the regularized cost function. Then, an output signal is provided based on the updated first vector. The second vector is updated based on the update of the first vector. An apparatus for adaptive signal processing is provided accordingly. The method and the apparatus are well compatible with existing adaptive signal processing. The convergence coefficients of the adaptive filter system become more stable. Moreover, impact of an extra penalty added to the cost function on a bias can be minimized, and the increased complexity of the system is very limited.

Method and apparatus for adaptive signal processing

The present disclosure provides a centralized power meter for a signal processing circuit, comprising: M sample buffers, each configured to buffer samples respectively from at least one of N sources, and trigger a request for power calculation of the buffered samples in response to the buffered samples, the request having a corresponding priority; a switch, configured to route the requests from the M sample buffers to one or more power calculation cores; the one or more power calculation cores, each configured to retrieve the samples from the sample buffer in an order of their corresponding priorities, in response to the routed requests, and to perform power calculation of the retrieved samples, wherein N and M are integers no less than 1, and N is no less than M. The present disclosure further provides a centralized power calculation method.

Centralized power meter and centralized power calculation method

Embodiments of the present disclosure provide an apparatus of reducing a peak-to-average ratio of a multi-carrier signal to be transmitted in a wireless communication system. The apparatus comprises a multi-carrier processing circuitry, a storage and a peak cancellation circuitry. The multi-carrier processing circuitry is configured to process a plurality of signals on respective carriers and to combine the processed plurality of signals into a multi-carrier signal to be transmitted. The multi-carrier processing circuitry is further configured to process an injected impulse to obtain an impulse response of the multi-carrier processing circuitry. The storage is configured to store the impulse response as a clipping pulse. The peak cancellation circuitry is configured to apply the clipping pulse to the multi-carrier signal to cancel a peak of the multi-carrier signal whose amplitude is over a predetermined threshold.

Method and apparatus for par reduction

A method for testing a multi-chip system with multiple ports includes determining a test path formed by connecting the multiple ports. The test path is determined in such a way that the internal logic circuit of each chip in the multi-chip system is bypassed. The method further includes injecting a test traffic to the test path, and receiving the test traffic from the test path.

Method for testing a multi-chip system or a single chip and system thereof

The present invention discloses a path switching method and apparatus in a network comprising at least a first path and a second path. For an incoming traffic flow, it is determined that any of tunnels on the first path of all levels into which the incoming traffic flow is multiplexed is of a failure status. The incoming traffic flow is then forwarded via the second path. Herein, for the first path, one or more traffic flows are multiplexed into a tunnel, and one or more higher level tunnels are multiplexed into a lower level tunnel.

Method and apparatus for path switching

Presented is an apparatusand methodsfor detecting any burst error condition on a network. The apparatusmeasures the intervalbetween arriving packetson a networkand storesa series of interval measurements for analysis. The apparatusalso provides a comparatorfor determining if a burst error conditionoccurred. The methodshifts the stored interval valuesbased on the arrivalof the next packet and its associated interval value and sumsa subset of the stored interval valuesfor comparison to a pre-configured periodto determine if a burst error conditionexists for too few packets. The methodprovides the sumof a separate subset of stored interval valuesto another comparatorfor comparison to a pre-configured periodto determine if a burst error conditionexists for too many packets.

Methods and systems for detecting burst traffic

A method and circuit is provided for determining a control voltage of a voltage controlled oscillator with fast frequency lock of a phase-locked loop and which is advantageous to the situation when an ultra-low frequency reference is used. The method and circuit determines a current error between a reference clock signal and a feedback clock signal, and checks if the error is larger than the threshold value which checks if an error sign indicator is set, i.e. the error has switched sign since startup of feedback loop; if the error sign indicator is not set, the circuit determines a divisor, k, using the current error, e, current control voltage, u, previous error e, and previous control voltage, u; however, if the error sign indicator is set the circuit determines a divisor, k, using stored values for the latest control voltage and error when the error was negative and stored values for the latest control voltage and error when the error was positive; furthermore, the method and circuit determines a control voltage step using the determined error divided by the divisor, k, and determines a new control voltage using the current control voltage, u, and the determined control voltage step.

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Beijing, China

Gan Wen