Cypress Semiconductor Corporation

Galen E Stansell

Eric N Mann

Monte F Mar

Frederick B Jenne

King Hong Kwan

James Paul Myers

John J Wunner

Igor Kouznetzov

Ken Fox

Timothy Wright

King Eric Kwan

Xiaolin Ouyang

Timothy V Wright

Tomasz Cewe

J Kenneth Fox

A programmable latch circuit () can include a volatile latch () that may regenerate a value determined by programmable section (). In a test operation, a variable current source (') can generate a current (IBASE) that can be mirrored in test sections (-and-) and compared to a current drawn by either programmable element (-) or (-) by a latching operation of volatile latch (). Variable current source (&#x2032;) can enable characterization of programmable elements (-or-) as well as adjustable test threshold limits. A program voltage (Vprog) applied to programmable elements (-or-) can be also be variable to allow for characterization of programmable elements (-and-) over a range of voltages.

Anti-fuse latch self-test circuit and method

A charge pump circuit can include a pump-up circuit having a first disable switch coupled between a pump-up output node and a first power supply node that is enabled and then disabled in response to a source current path between the pump-up node and a second power supply node being disabled, and a source off switch coupled in series with the first disable switch that is enabled in response to the source current path being disabled. The charge pump circuit can also include a pump-down circuit having a second disable switch coupled between a pump-down output node and the second power supply node that is enabled and then disabled in response to a sink current path between the pump-down node and a first power supply node being disabled. A sink off switch can be coupled in series with the second disable switch that is enabled in response to the sink current path being disabled.

Charge pump circuit and method for phase locked loop

Disclosed is a high voltage switch circuit that can include a first well bias switch configured to track the greater of an input voltage and a supply voltage, a voltage comparator configurable to compare the input voltage to a predetermined reference voltage, and a second well bias switch having a control input coupled to an output of the comparator.

Well bias architecture for integrated circuit device

A test circuit can test a status of a group of non-volatile elements. A current flowing to the group of non-volatile elements can be compared against a reference value. If the current is determined to be outside of a predetermined range, the non-volatile elements can be determined to be programmed. In particular embodiments, non-volatile elements can be sections of differential one-time programmable anti-fuse latch memory elements.

Device and method for sensing programming status of non-volatile memory elements

A programmable latch circuit () can include a programmable data circuit () with a data load path () that can enable a data value to be recalled into a volatile latch (). A data load path () can be formed with devices (P-P) having low threshold voltages. Data can be loaded via data load path at lower power supply voltages levels, such as on power-on and/or reset operations. Other embodiments disclose, self-test circuits, full redundancy capabilities, and resistors for limiting current draw in an anti-fuse program operation.

Anti-fuse latch circuit and method including self-test

In one embodiment, a control loop in an electrical circuit includes a variable feed-forward circuit configured to determine a setting of a variable oscillator that would result in a frequency of a first signal approximating a frequency of a second signal. The setting may be used to control the variable oscillator at a time when a phase error between the first signal and the second signal is negligibly small (e.g., substantially zero), thus allowing for relatively short loop convergence time.

Method and apparatus for converging a control loop

In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Robust clock circuit architecture

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a reference input and a feedback signal. The second circuit may be configured to generate the feedback signal according to a plurality of moduli in response to the output signal, a first control signal and a second control signal. The frequency of the output signal may be modulated in response to the second control signal.

Multi-modulus counter in modulated frequency synthesis

A circuit configured to generate an output signal having a first frequency in response to a clock signal having a second frequency. The output signal may be in a first state and a second state for an equal number of half-cycles of the clock signal.

Loadable divide-by-N with fixed duty cycle

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.

Clock generator with programmable two-tone modulation for EMI reduction

A delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.

Clock circuit for generating a delay

A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal. The sampled lock signal, and the input clock signal (formed from the PLL output reference signal) are provided on respective input terminals of the AND gate. The output of the AND gate defines the output clock signal.

Enabling clock signals with a phase locked loop (PLL) lock detect circuit

A circuit for latching inputs and enabling outputs on a bidirectional pin using a PLL lock detect circuit is disclosed. A PLL lock detect circuit generates an active lock control signal when an output reference signal is phase locked relative to an input reference signal applied to a phase locked loop (PLL) circuit. A latch and enable circuit is responsive to this lock control signal to latch the input signal (off of the pin), and, thereafter, enable output of an output signal onto the bidirectional pin. The latch and enable circuit includes a data latch to store the input signal when the lock control signal goes to an active state. The latch and enable circuit also includes a delay circuit to delay the lock control signal to produce a delayed lock control signal, and a tristateable output driver that is tristated when the delayed lock control signal is inactive, but, operates to pass (i.e., enable) the output signal to the bidirectional pin when the delayed lock control signal is active.

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Kirkland, WA, United States of America

Galen E Stansell