Cray Research, Inc.

Galen C Flunker

Stephen E Nelson

David L Duxstad

Alan J Schiffleger

Richard D Pribnow

George W Leedom

A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Method for adjusting clock skew

An apparatus for adjusting signal delay includes an input for receiving a signal to be delay adjusted. A delay circuit is connected to the input means for providing a plurality of selectable signal paths for various delay amounts for producing a delay adjusted signal therefrom. A delay selection circuit is connected to the delay circuit for selecting the signal path so as to select a delay amount and an output provides the delay adjusted signal to a load. Skew compensation is employed on the input and individually on each output to compensate for clock distribution network skew and intracircuit skews, respectively.

Method of adjusting for clock skew

The present invention provides a vector processing computer system adapted for real-time I/O. The present invention combines a rotating priority interrupt scheme, dedicated real-time interrupt lines for each processor, and access to privileged communication/control modes of operation for processors operating in real-time to create a flexible hardware design adaptable for use in many different real-time applications.

Real time I/O operation in a vector processing computer system by

An apparatus precisely adjusts the delay of a clock signal so as to reduce clock skew. The electronically programmable skew adjustment can be self-contained within a single IC package. The apparatus has an input for receiving a signal to be delay adjusted, delay elements including capacitive delay elements for providing multiple signal paths of various delays, delay selection circuitry for selecting the signal paths so as to select a delay amount, and an output to provide the delay adjusted signal to a load.

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Menomonie, WI, United States of America

Galen C Flunker