Intel Corporation

Gal Yedidia

Ziv Kabiry

Nausheen Ansari

Reuven Rozic

A system can include a host router comprising connection manager logic, a display port adapter, and a display port adapter register to comprise display port adapter register values. A display port source device comprises a display port transmitter connected to the display port adapter. A display port configuration data (DPCD) register comprises display port configuration register values for the display port, the display port transmitter to write to the DPCD register. The display port adapter is to map DPCD register values to the display port adapter register. The connection manager logic is to receive a notification message requesting bandwidth allocation for the display port transmitter, determine an allocated bandwidth for the display port transmitter, and write the allocated bandwidth into the display port adapter register.

Bandwidth management allocation for displayport tunneling

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

High speed interconnect symbol stream forward error-correction

An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.

Advanced link power management for displayport

In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.

Display link power management using in-band low-frequency periodic signaling

A universal serial bus (USB) router can include a display port input device to receive a display port signal. The display port input device can include display port link layer parser circuitry to identify display port control or data information from the received display port signal, USB packet construction circuitry to construct a USB packet comprising the display port control or data information identified by the display port link layer parser circuitry, and a USB switch to transmit the USB packet comprising the display control or data information over a USB link. A display port output device can include display port packetizer circuitry to construct a display port packet from the display port control or data information from the USB packet, and display port output circuitry to output the display port packet across a display port link.

Transmitting displayport 2.0 information using USB4

Techniques for synchronizing a display transmitter and display panel are described. An example display panel includes a timing controller to receive display data from a transmitter and render the display data on a display screen of the display panel. The display panel is in a first clock domain and the transmitter is in a second clock domain which is derived separately from the first clock domain. The display panel also includes a time code generator to generate a first display time code and a frequency adjuster to receive a second display time code from the transmitter. The frequency adjuster adjusts the clock frequency of the display panel based on the first display time code and the second display time code.

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Haifa, Israel

Gal Yedidia