Toshiba Memory Corporation

Kioxia Corporation

Gaku Sudo

Tadashi Kai

Masahiko Nakayama

Kazumasa Sunouchi

Jun Nogami

Megumi Ishiduki

Jun Fujiki

Tadashi Iguchi

Takashi Ishida

Yumiko Miyano

Murato Kawai

Koji Matsuo

Tatsuro Shinozaki

Kenzo Manabe

Masanobu Baba

A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Nonvolatile storage device

According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

Semiconductor device

A semiconductor device according to an embodiment, includes a stacked body, a plurality of first terraces, a second terrace, a plurality of interconnects, a plurality of conductive bodies. The stacked body includes a plurality of electrode layers. The stacked body includes a stairstep portion at an end portion of the stacked body. The plurality of first terraces are provided in the stairstep portion. The second terrace is provided in the stairstep portion. The plurality of interconnects are provided from the second terrace to the plurality of first terraces. The plurality of interconnects contact one of the plurality of electrode layers at the stairstep portion. The plurality of conductive bodies are provided above the second terrace. The plurality of conductive bodies extend in a stacking direction of the stacked body. The conductive bodies contact the interconnects above the second terrace.

Semiconductor device and method for manufacturing the same

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.

Semiconductor device and method for manufacturing same

According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first insulating region, and a memory portion. The first connector extends in a first direction. The first conductive layer is electrically connected to the first connector, and includes a first planar region, a first overlap region, a first side surface region, and a first crossing side surface region. The second connector extends in the first direction. The second conductive layer is electrically connected to the second connector, and includes a second planar region, a second overlap region, a second side surface region, and a second crossing side surface region. The first insulating region is provided between the first and second conductive layers. The memory portion is connected to the first and second planar regions.

Nonvolatile semiconductor memory device and method for manufacturing the same

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Yokkaichi, Japan

Gaku Sudo