Kabushiki Kaisha Toshiba

Toshiba America Electronic Components, Inc.

International Business Machines Corporation

Gaku Sudo

Haining S Yang

Ramachandra Divakaruni

Yoshiaki Asao

Kazuyuki Higashi

Byeong Yeol Kim

Iwao Kunishima

Susumu Shuto

Junedong Lee

Hironobu Furuhashi

Nobutaka Watanabe

A memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which plural pairs of a first crystal layer made of a first compound and a second crystal layer made of a second compound are alternately stacked. An average composition of the entire resistance change film or an arrangement pitch of the first crystal layers and the second crystal layers are mutually different among the n resistance change films.

Memory device

According to one embodiment, a method for manufacturing a semiconductor device, includes preparing a structure body. In the structure body, a fin extending in a first direction is formed on an upper surface of a semiconductor substrate, a lower-side mask member is provided on the fin, and an upper-side mask member that is wider than the fin and the lower-side mask member is provided on the lower-side mask member. The method includes implanting an impurity into the semiconductor substrate with the upper-side mask member and the lower-side mask member as a mask, removing the upper-side mask member, forming a gate insulator film on a side surface of the fin, forming a conductive film that covers the fin and the lower-side mask member, forming a mask for gate having a pattern extending in a second direction, and removing selectively the conductive film to form a gate electrode.

Method for manufacturing fin semiconductor device using dual masking layers

An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.

Integrated circuit device and method for manufacturing same

According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A protrusion is formed at a portion of the each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction of the arrangement. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. In the each of the interconnects, the portion having the recess is separated from portions on two sides of the portion having the recess and is separated also from the portion having the protrusion.

According to one embodiment, a semiconductor device includes, a semiconductor substrate including a plurality of fins formed in an upper surface of the semiconductor substrate in a first region to extend in a first direction, a first gate electrode extending in a second direction intersecting the first direction to straddle the fins, a first gate insulating film provided between the first gate electrode and the fins, a second gate electrode provided on the semiconductor substrate in the second region; and a second gate insulating film provided between the semiconductor substrate and the second gate electrode. A layer structure of the first gate electrode is different from a layer structure of the second gate electrode.

Semiconductor device and method for manufacturing same

A method for manufacturing a semiconductor device includes forming a mask film on a partial region of a semiconductor substrate; forming a mask member above the semiconductor substrate in both the region where the mask film is formed and a region where the mask film is not formed; patterning the mask film and an upper portion of the semiconductor substrate by performing etching using the mask member as a mask. The method further includes removing part of the patterned upper portion of the semiconductor substrate by performing etching using the patterned mask film as a mask.

Method for manufacturing semiconductor device

According to one embodiment, an integrated circuit device includes interconnects and a contact via. The interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A protrusion is formed at a portion of the each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. In the each of the interconnects, the portion having the recess is separated from portions on two sides of the portion having the recess and is separated also from the portion having the protrusion.

According to one embodiment, a method for manufacturing a semiconductor device includes forming a fin in an upper surface of a semiconductor substrate to extend in a first direction, forming a mask film, making a plurality of first trenches in the mask film to extend in a second direction to reach the fin, filling sidewall members into the first trenches, making a second trench by removing the mask film from a portion of a space between the sidewall members, forming a gate insulating film and a gate electrode on a surface of a first portion of the fin disposed inside the second trench, making a third trench by removing the mask film from the remaining space between the sidewall members, and causing a second portion of the fin disposed inside the third trench to become a conductor.

According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.

Method of manufacturing semiconductor device

According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to the each of the interconnects. A protrusion is formed at a portion of each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. The portion having the recess is separated from portions on two sides thereof and is separated also from the portion having the protrusion.

Integrated circuit device with interconnects arranged parallel to each other and connected to contact via, and method for manufacturing same

According to one embodiment, a method for manufacturing a semiconductor device includes forming a depression in an upper portion of a semiconductor substrate, placing a sacrificial material in the depression, forming a plurality of fins extending in one direction and arranged periodically by selectively removing the semiconductor substrate and the sacrificial material, forming a device isolation insulating film in a lower portion of space between the fins, removing the sacrificial material, forming a gate insulating film on an exposed surface of the fin, and forming a gate electrode. The gate electrode extends in a direction crossing the one direction so as to straddle the fin on the device isolation insulating film.

According to one embodiment, a manufacturing method of a semiconductor device includes forming a lower mask film on a semiconductor substrate. The method includes forming a barrier film in a first area. The method includes forming an upper mask film. The method includes removing an upper mask member and leaving a lower mask member in the first area and removing the upper mask member and the lower mask member in the second area. The removing is performed by etching in a condition in which an etching rate of the upper mask member and an etching rate of the lower mask member are higher than that of the barrier member. The method includes forming a conductive film. The method includes selectively removing the conductive film by performing etching in a condition in which an etching rate of the conductive film is higher than that of the lower mask member.

Manufacturing method of semiconductor device

According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.

Semiconductor memory device and method for manufacturing same

A method of manufacturing a semiconductor device according to an embodiment of the present invention forms at least one pair of gate electrodes having end portions opposed to each other across a gap. The method includes forming a gate insulator and a gate electrode layer on a substrate in order, forming a first anti-reflection coating and a first resist on the gate electrode layer in order, exposing and developing the first resist, etching the gate electrode layer, using the first resist or the first anti-reflection coating as a mask, to remove the gate electrode layer from a region for forming the gap, thereby forming a hole penetrating the gate electrode layer, forming a second anti-reflection coating and a second resist on the gate electrode layer where the hole has been formed, in order, exposing and developing the second resist, and etching the gate electrode layer, using the second resist or the second anti-reflection coating as a mask, to form, from the gate electrode layer, the at least one pair of gate electrodes having the end portions opposed to each other across the gap.

Growing community of inventors

Kanagawa-ken, Japan

Gaku Sudo