Lsi Logic Corporation

Gagan V Gupta

Frank Henry Worrell

Daniel R Watkins

Venkat Mattela

Rene Vangemert

Kosala Abeywickrema

Satish Venugopal

Kumar Bhattaram

Mengchen Yu

A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling the processor in response to an instruction requiring data buffered by the register and the register status being in the invalid state.

Processor pipeline stall based on data register status

An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]&#x2212;S*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sis the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]&#x2212;2S[j]S, where W[j] is the estimated partial remainder and Sis the estimated result generated during the current iteration, j. A shift register shifts the value of the estimated result, S, to generate &#x2212;S&#xb7;2, which is summed with the result from the first summing device to generate the estimated partial remainder for the square root mode.

Floating point divide and square root processor

A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.

Data-cache data-path

The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design. The present invention describes the method and apparatus to reverse-synthesize gate netlist level definitions into RTL definitions by parsing and analyzing the gate netlist level definition, generating an equivalent RTL definition, and verifying correctness of the RTL definition.

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Union City, CA, United States of America

Gagan V Gupta