Microsoft Technology Licensing, LLC

Gagan Gupta

Douglas Christopher Burger

Thomas Philip Speier

Karin Strauss

Rodney Wayne Smith

Bichlien Hoang Nguyen

David Tennyson Harper, Iii

David T Harper

Richard P Rouse

Abolade Gbadegesin

Michael Scott McIlvaine

Aaron L Smith

Yusuf Cagatay Tekmen

Jason Stewart Wohlgemuth

Artur Klauser

Brian Stempel

Douglas M Carmean

Rathijit Sen

Derek Chiou

Jake Smith

Robert Douglas Clancy

Melinda Joyce Brown

Kiran Ravi Seth

Matthew David Turner

Cody D Hartwig

Soheil Ebadian

Hossein Golestani

David T Iii Harper

Polymers synthesized by solid-phase synthesis are selectively released from a solid support by reversing the bias of spatially addressable electrodes. Change in the current and voltage direction at one or more of the spatially addressable electrodes changes the ionic environment which triggers cleavage of linkers that leads to release of the attached polymers. The spatially addressable electrodes may be implemented as CMOS inverters embedded in an integrated circuit (IC). The IC may contain an array of many thousands of spatially addressable electrodes. Control circuity may independently reverse the bias on any of the individual electrodes in the array. This provides fine-grained control of which polymers are released from the solid support. Examples of polymers that may be synthesized on this type of array include oligonucleotides and peptides.

Reversing bias in polymer synthesis electrode array

Photon generating substrates for light-directed oligonucleotide synthesis are disclosed. Light is generated within a solid-state stack that supports growing oligonucleotides. The light may be generated by microLEDs, a pass-through liquid crystal panel, or an LCoS system. Light passes through a transmissive layer on which growing oligonucleotides are attached. Patterning of the light is controlled by selective activation of the microLEDs or by selective control of the transparency of a liquid crystal layer. Photolabile blocking groups are selectively removed by exposure to patterned light emitted from the photon generating substrate.

Photon generating substrates for oligonucleotide synthesis

A reach matrix scheduler circuit for scheduling instructions to be executed in a processor is disclosed. The scheduler circuit includes an N&#xd7;R matrix wake-up circuit, where 'N' is the instruction window size of the scheduler circuit, and 'R' is the 'reach' within the instruction window of the matrix wake-up circuit, with &#x2018;R&#x2019; being less than &#x2018;N&#x2019;. A grant line associated with each instruction request entry in the N&#xd7;R matrix wake-up circuit is coupled to &#x2018;R&#x2019; other instruction entries among the &#x2018;N&#x2019; instruction entries. When a producer instruction in an instruction request entry is ready for issuance, the grant line associated with the instruction request entry is activated so that any other instruction entries coupled to the grant line (i.e., within the 'reach' of the instruction request entry) that consume the produced value generated by the producer instruction are &#x201c;woken-up&#x201d; and subsequently indicated as ready to be issued.

Reach matrix scheduler circuit for scheduling instructions to be executed in a processor

Embodiments described herein are directed to a microarchitecture modeling tool configured to model and analyze a microarchitecture using a dependency graph. The dependency graph may be generated based on an execution trace of a program and a microarchitecture definition that specifies various features and/or characteristics of the microarchitecture on which the execution trace is based. The dependency graph includes vertices representing different microarchitectural events. The vertices are coupled via edges representing a particular dependency therebetween. The edges are associated with a cost for performing microarchitectural event(s) corresponding to the vertices coupled thereto. The dependency graph also takes into account various policies for structural hazards of the microarchitecture. The microarchitecture modeling tool analyzes the costs associated with each of the edges to determine a design metric of the microarchitecture. A user is enabled to modify various features of the dependency graph to analyze different design choices and/or optimizations to the microarchitecture.

Performance modeling and analysis of microprocessors using dependency graphs

Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.

Coupling wide memory interface to wide write back paths

Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address. In some embodiments, any address translation errors encountered are raised to an appropriate exception level, and may be raised synchronously or asynchronously with respect to an operation performed when the speculative translation instruction is executed.

Performing speculative address translation in processor-based devices

Systems and methods are disclosed for allocating resources to contexts in block-based processor architectures. In one example of the disclosed technology, a processor is configured to spatially allocate resources between multiple contexts being executed by the processor, including caches, functional units, and register files. In a second example of the disclosed technology, a processor is configured to temporally allocate resources between multiple contexts, for example, on a clock cycle basis, including caches, register files, and branch predictors. Each context is guaranteed access to its allocated resources to avoid starvation from contexts competing for resources of the processor. A results buffer can be used for folding larger instruction blocks into portions that can be mapped to smaller-sized instruction windows. The results buffer stores operand results that can be passed to subsequent portions of an instruction block.

Executing multiple programs simultaneously on a processor core

Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction. This reach-based explicit naming architecture does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is not limited to explicit naming of consumer instructions only within the same instruction block of the producer instruction.

Reach-based explicit dataflow processors, and related computer-readable media and methods

Enabling peripheral device messaging via application portals in processor-based devices is disclosed herein. In one embodiment, a processor-based device comprises a processing element (PE) including an application portal configured to logically operate as a message store, and that is exposed as an application portal address within an address space visible to a peripheral device that is communicatively coupled to the processor-based device. Upon receiving a message directed to the application portal address from the peripheral device, an application portal control circuit enqueues the message in the application portal. In some embodiments, the PE may further provide a dequeue instruction that may be executed as part of the application, and that results in a top element of the application portal being dequeued and transmitted to the application. Some embodiments may provide further mechanisms for sending success and/or failure notifications, and/or for informing the application that the message has been enqueued.

Enabling peripheral device messaging via application portals in processor-based devices

Techniques described herein are directed to ensuring register data consistency between different instruction blocks. For example, a block-based processor renames registers during block decode, but delays the update of a logical register-to-physical register mapping utilized by other instruction blocks until it is determined that a write instruction configured to write to a logical register commits. Alternatively, the processor renames registers during block decode and updates the mapping accordingly. However, the update is negated (e.g., rolled back) if the write instruction is not executed. Still further, the processor may analyze the instructions in the block to determine instructions configured to write to a logical register but that will not execute due to a mismatched predicate. Based on the determination, the block-based processor ensures data consistency by copying data from a previously-assigned register to a newly-assigned register. Techniques may also be utilized to assist the block-based processor in determining such instructions.

Register renaming-based techniques for block-based processors

Operand-based reach explicit dataflow processors, and related methods and computer-readable media are disclosed. The operand-based reach explicit dataflow processors support execution of a producer instruction that explicitly names a target consumer operand of a consumer instruction in a consumer operand encoding namespace of the producer instruction. The produced value from execution of the producer instruction is provided or otherwise made available as an input to the named target consumer operand of the consumer instruction as a result of processing the producer instruction. The target consumer operand is encoded in the producer instruction as an operand target distance relative to the producer instruction. Instructions in an instruction stream between the producer instruction and the targeted consumer instruction that have no operands do not consume an operand reach namespace in the producer instructions. This provides for a deeper explicit consumer naming reach for a given bit size of the operand reach namespace.

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

Systems and methods are disclosed for executing instructions with a block-based processor. Instructions can be executed in any order as their dependencies arrive, but the individual instructions are committed in a serial fashion. Further, exception handling can be performed by storing transient state for an instruction block and resuming by restoring the transient state. This allows programmers to see intermediate state for the instruction block before the subject block has committed. In one examples of the disclosed technology, a method of operating a processor executing a block-based instruction set architecture includes executing at least one instruction encoded for an instruction block, responsive to determining that an individual instruction of the instruction block can commit, advancing a commit frontier for the instruction block to include all instructions in the instruction block that can commit, and committing one or more instructions inside the advanced commit frontier.

Growing community of inventors

Bellevue, WA, United States of America

Gagan Gupta