Conexant Systems, Inc.

Trident Microsystems (far East) Ltd.

Entropic Communications, Inc.

Gadi Kalit

Shachar Kons

Eran Arad

Yoav GoldenBerg

Shimon Gur

Chi-ping Nee

Ronen Hershkovitz

Prasad Shamain

Abraham Krieger

Ladd S El Wardani

Shimon Tzukerman

A satellite signal demodulator is configured to use frequency-based channel scanning to sense the presence of a channel and to obtain the frequency profile of the channel. Once the channel is identified and the profile is obtained, channel extraction is used to identify the frequency parameters for a given channel. A coarse parameter estimation is performed to obtain a coarse estimate of the symbol rate (SR) and the center frequency (f) of the channel. The coarse estimation can then be followed by a fine estimation of the symbol rate and center frequency (f), using a bit tracking loop (BTL) lock indicator.

Systems and method for frequency based satellite channel scanning

An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing. The decoder may also employ a novel method for generating check node to bit node messages through a prescribed series of pair-wise computations.

Efficient decoders for LDPC codes

A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.

Multi-channel LDPC decoder architecture

A system for use in transmitting digital data includes a modulation element that receives block of digital data and modulates each block using one of at least two modulation types, such as QPSK and k-QAM, where k is a power of 2. The system also includes an automatic power control element that applies a selected gain value to each of the blocks of data before transmission. The automatic power control element selects each of the gain values from a group of at least two predetermined gain values, each of which corresponds to one of the modulation types. In general, the modulation types have different associated average power levels, and the power control element selects the gain values to maintain substantially constant average transmission power level among all of the blocks of data.

Automatic power control in a data transmission system

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Nahariya, Israel

Gadi Kalit