National Semiconductor Corporation

Gadi Erlich

Ohad Falik

Gideon Intrater

Chaim Bendelac

Jonathan Levy

Aharon Ostrer

Dan Biran

Yair Baydatch

Daivid Briet

Hezi Friedman

An apparatus and method for providing a secure universal serial bus (USB) is disclosed. The secure USB comprises a secure channel for transferring data. A secure USB domain device is coupled to a host computer or is embedded within a host computer. The secure USB domain device comprises a USB memory device, a USB processor, a USB host controller, and an internal USB bus coupled to each of the elements of the secure USB domain device. The elements of the secure USB domain device are not accessible by the host computer. The secure USB domain device blocks the transmission of confidential information, enables the transmission of non-confidential information, and enables the transmission of encrypted confidential information.

Secure universal serial bus

A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

Processor core which provides a linear extension of an addressable

Binary multiplication is performed with existing data processing apparatus to which only minor modifications are required. One operand and a partial product are stored in existing latches of a CPU. The second operand is stored in a shift register which is added to the CPU. The data in the shift register is shifted from the LSB to the MSB, with a '0' being loaded into the LSB. As the bits in the first operand are designated in sequence, the value of the partial product is increased by the value in the shift register if the designated bit is a '1'. After the sequencing has designated all the bits of the first operand, the partial product is taken to be the product of the multiplication.

Binary multiplication implemented by existing hardware with minor

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Mosha Hadar Am, Israel

Gadi Erlich