National Semiconductor Corporation

Analog Devices,inc.

Analog Devices International Unlimited Company

Edgewater Computer Systems, Inc.

Engim, Incorporated

Analog Devices Global Unlimited Company

Gabriele Manganaro

Matthew Louis Courcy

Gil Engel

Athanasios Ramkaj

Filip Tavernier

Martin Clara

Hajime Shibata

Franco Maloberti

Lawrence A Singer

Wenhua William Yang

Yunzhi Dong

Kimo Tam

David Nelson Alldred

Siddharth Devarajan

Sharvil Pradeep Patil

Paul F Ferguson

Jipeng Li

Nevena Rakuljic

Front-end circuitry is difficult to design for high sample rate, wide bandwidth receivers with high performance requirements on noise and linearity. One exemplary front-end circuitry is integrated on-chip with the RF ADC in a receiver, and the circuitry implements ESD protection, attenuation, and gain. The circuitry includes a multi-tap filter with LC circuits, and the filter implements a highly linear filter. Advantageously, the capacitors in the LC circuits are also used for ESD protection. Additionally, tunable attenuator cells are implemented across the multi-tap filter to provide a wide range of variable attenuation. The circuitry can further include a fixed or variable gain stage at the output. The resulting circuitry offers variable gain and attenuation while meeting bandwidth, noise, and linearity requirements.

Front-end for receivers with RF sampling ADCS

High-performance radio frequency analog-to-digital converters (RF ADCs) demand high bandwidth, high linearity, and low noise input amplifiers. A Class-AB amplifier, including common-gate transistor devices and common-source transistor devices operating in parallel, offers high bandwidth and high linearity, while offering lower power operation when compared to Class-A amplifiers. The Class-AB amplifier can be followed by a Class-AB unity gain buffer comprising common-source transistor devices to provide additional isolation for the RF ADC from the circuitry preceding the Class-AB amplifier.

Amplifiers for RF ADCS

Non-idealities of input circuitry of a receiver signal chain can significantly degrade the overall performance of the receiver signal chain. To meet high performance requirements, the input circuitry is typically implemented with power hungry circuitry in a different semiconductor technology from the analog-to-digital converter that the input circuitry is driving. With suitable optimization techniques, performance requirements on the input circuitry can be reduced while meeting target performance of the receiver signal chain. Specifically, optimization techniques can compensate for input frequency-dependent properties and/or amplitude-dependent properties of the input circuitry. In some cases, reducing performance requirements on the input circuitry means that the input circuitry can be implemented in the same semiconductor technology as the analog-to-digital converter.

Receiver signal chains with low power drivers and driver optimization

A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.

Reducing residue signals in analog-to-digital converters

Circuits are used to sense and compensate or mitigate the imbalance errors, hence restoring the intended benefits of differential processing. In particular, the impedance mismatch between the positive and negative branches of a balanced system is sensed by digitizing an error voltage developed by injecting suitable common mode stimuli. The mismatch is then trimmed out by introducing and properly setting up a digitally controlled impedance that counters the original impedance mismatch and hence rebalances the signal path on-situ and prior to exercising the signal processing chain.

Circuits for on-situ differential impedance balance error measurement and correction

Reducing distortions in a digital-to-analog converter is a challenge for circuit designers. For current steering digital-to-analog converters (DACs), a quad switching scheme has been used to remove code-dependent glitching which is otherwise present in dual switching schemes. However, due to various impairments in the circuit, e.g., mismatches in the transistors, some code-dependent distortions remain even when a quad switching scheme is implemented. To address this issue, the quad switching scheme can be randomized to improve dynamic linearity while relaxing driving circuitry design and power constraints. Advantageously, randomization reduces the code dependency of the distortions and makes the distortions appear more noise-like at the output of the DAC.

Randomized quad switching

Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.

Limiting aging effects in analog differential circuits

The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Complementary switches in current switching digital to analog converters

The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.

Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter

A method for performing parallel digital-to-analog conversion of an n-bit digital input data signal at a frequency of fincluding receiving the n-bit digital input data signal; generating M&#x2212;1 delayed input data signals, M being the number of parallel conversions channels, the M&#x2212;1 delayed input data signals having respective increasing amount of unit delay, the digital input data signal and the M&#x2212;1 delayed input data signals forming M digital signals; holding the M digital signals for a first time period; performing a data transformation of the M digital signals using an M&#xd7;M Hadamard matrix; generating M (n+m)-bit transformed digital data signals; converting each of the M transformed digital data signals to M analog signals; and performing a reverse data transformation of the M analog signals based on the M&#xd7;M Hadamard matrix to generate an output analog signal indicative of the n-bit digital input data signal.

Parallel digital-to-analog-converter

A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.

Regulated switch driving scheme in switched-capacitor amplifiers with opamp-sharing

A transresistance amplifier circuit includes an input terminal receiving an input current, an output terminal providing an output voltage indicative of the input current, a first bias current source providing a first bias current to the input terminal, a first transistor, a second transistor, and a biasing circuit. The first transistor is coupled between the output terminal and the input terminal and controlled by a first bias voltage. The second transistor is coupled between a first supply voltage and the output terminal and controlled by a second bias voltage. The biasing circuit generates the first bias voltage for the first transistor for imposing a first voltage at the input terminal. The first voltage is equivalent to a selected voltage of an application circuit and the biasing circuit generates the first bias voltage in a manner so as to allow the first voltage to track variations in the selected voltage.

Transresistance amplifier

A calibration circuit for a current source cell includes a reference current source and a transresistance amplifier forming a feedback loop for calibrating the output current of the current source cell. The reference current source supplies a reference current to a first node switchably connected to the current output node of the current source cell. The transresistance amplifier has an input terminal coupled to the first node and an output terminal switchably connected to a calibration node of the current source cell. With the calibration circuit coupled for calibration, an input current develops at the first node being the difference between the output current of the current source cell and the reference current. The transresistance amplifier receives the input current and generates an output voltage for driving the calibration node. The output voltage has a value operative to nullify the difference between the output current and the reference current.

Analog calibration of a current source array at low supply voltages

A current source cell includes a current source providing a first current where the first current can be calibrated, first and second switches coupled to steer the first current to respective first and second output terminals in response to respective first and second control signals, and a latch circuit generating the first and second control signals. The latch circuit drives the first and second control signals to a first logical state to cause the first and second switches to open. The first current is then calibrated. After calibration, the latch circuit drives the first and second control signals to have logical states that correspond to a data signal as triggered by a clock signal where the first and second control signals have inverse logical states. One of the first and second switches is closed to steer the first current to a respective one of the first and second output terminals.

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Boxborough, MA, United States of America

Gabriele Manganaro