Intel Corporation

Gabriele Boschi

Alessandro Campinoti

Jennifer Wang

Nabajit Deka

Divya Gupta

Roger May

Gabriele Paoloni

Srajudheen Makkadayil

Rekha Manjunath

Matteo Salardi

Bakshree Mishra

A fault detector has a processor configured to receive, during a register write event, first data that are to be stored on a first register; determine a first encoded value from the first data using an encoding operation; receive second data from the first register from one or more bit locations on which the first data were to be stored; determine a second encoded value from the second data using the encoding operation; and compare the first encoded value and the second encoded value. If the first encoded value is the same as the second encoded value, the fault detector operates according to a first operational mode; and if the first encoded value is different from the second encoded value, the fault detector operates according to a second operational mode.

Register fault detector

Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

Two die system on chip (SoC) for providing hardware fault tolerance (HFT) for a paired SoC

Technologies for ensuring functional safety of an electronic device include receiving data by a primary and secondary hardware unit and performing a function on the data. Each of the primary and secondary hardware unit perform the same function on their respective set of data to generate corresponding results. A determination is made whether the hardware units are synchronized and the results can be compared. If so, the results are compared and an alert is generated if the results do not match.

Technologies for ensuring functional safety of an electronic device

In embodiments, a system may comprise a circuit component to perform a function; and a supervisor component (e.g., a safety component) coupled to the circuit component to monitor proper functioning of the circuit component. The circuit component may be configured to initiate provision of diagnostic information to the supervisor component, or to indicate to the safety component whether the circuit component will be responsive to a query from the safety component for diagnostic information.

Electronic component monitoring method and apparatus

Growing community of inventors

Lucca, Italy

Gabriele Boschi