Silicon Laboratories Inc.

Cirrus Logic Inc.

Gabriel Vogel

John L Melanson

Jeffrey Donald Alderson

Alan Lee Westwick

Donald E Alfano

Dazhi Wei

Kafai Leung

Nitin Kwatra

Alvin Chuck Storvik

Bradley Allan Lambert

Ryan A Hellman

Xiaoling Guo

Donelson Arthur Shannon

Anthony Louviere

Yuchao Chen

Des Peter Howlett

Isochronous channels may be used for transporting non-isochronous data between components in an electronic device, such as when non-isochronous data is aggregated from multiple non-isochronous data streams to achieve a high peak-to-average bandwidth. The aggregated non-isochronous data sources may include data streams from general-purpose communications interfaces for interconnecting components or sub-systems of components within an electronic device. For example, I2C networks for control and programming of components may be connected to other I2C networks through an isochronous channel, such as a differential pair of Soundwire SWI3S wires.

Communicating non-isochronous data over an isochronous channel

Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.

Device calibration for isochronous channel communication

An active noise cancellation (ANC) system including a selectable decimation rate decimator that receives an oversampled digital input and has an input that selects the decimation rate, a filter that receives an output of the decimator, and a selectable interpolation rate interpolator that receives an output of the filter and has an input that selects the interpolation rate. The selectable decimation rate decimator and the selectable interpolation rate interpolator operate to provide a selectable sample rate for the filter based on the selected decimation and interpolation rates. The filter may be an anti-noise filter, feedback filter, and/or a filter that models an acoustic transfer function of the ANC system. Rate selection may be static, or dynamically controlled based on battery or ambient noise level. A ratio of the decimation rate and the interpolation rate is fixed independent of the dynamically controlled decimation and interpolation rates.

Active noise cancellation (ANC) system with selectable sample rates

A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request.

Controlling communication of a clock signal to a peripheral

A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.

Low power retention flip-flops

A method is disclosed for generating a sequential pattern of motor control instructions under control of a microcontroller for the purpose of controlling a motor. A pattern of motor control instructions is stored in a memory. A timing circuit is operable to generate a periodic output sync signal. The microcontroller is operable to initiate a sequential Read operation of the memory so as to cause sequential reading and output of motor control instructions from the memory in a predetermined order. Each of the read motor control instructions is then stored in a pre-load buffer after output from the memory. The contents of the pre-load buffer is then transferred to an output buffer in synchronization with the output sync signal, wherein the output of motor control instructions from the memory is not required to be periodic.

MCU based motor controller with pre-load register and DMA controller

A system for monitoring interrupts to a processor includes a multiplexer having a plurality of inputs connected to receive various analog inputs. The multiplexer further has an output which is programmably connected to one of the plurality of inputs responsive to a control signal. An analog to digital converter is connected to the output of the multiplexer for converting an analog signal at the output to a digital signal. An auto-scan block generates the control signal provided to the multiplexer. The control signal selects ones of the plurality of inputs of the multiplexer for connection to the output in a programmably defined order.

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Austin, TX, United States of America

Gabriel Vogel