Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Nxp B.v.

Edgcore Technology, Inc.

Edge Computer Corporation

Gabriel R Munguia

Nicholas Julian Richardson

Joseph Charles Circello

Peter Chambers

Lonnie Calvin Goff

Daniel M McCarthy

Ned D Garinger

Brian Logsdon

A computer-based software task management system includes an index register configured to store a data register pointer for pointing to a data register. A Task ID register is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a task ID memory.

Hardware register access via task tag ID

Among the embodiments of the present invention is a processor ( ) having a number of registers in a register bank ( ). The registers include a general purpose register ( ) and a stack pointer register ( ) having a common register name. Processor ( ) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register ( ) under a first condition and with stack pointer register ( ) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Selective access to multiple registers having a common name

The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent, a retry identification register, and a completion counter. The initiator PCI agent is adapted to couple to a PCI bus and communicate with a target PCI agent via the PCI bus by initiating a data transaction. The retry identification register is coupled to the initiator PCI agent. The retry identification register is adapted to store a target address and a transaction type corresponding to the target PCI agent when the target PCI agent issues a retry to the initiator PCI agent. The completion counter is coupled to the initiator PCI agent and is adapted to measure a latency period of the target PCI agent. The completion counter couples the latency period to the initiator PCI agent such that the initiator PCI agent efficiently completes a subsequent access corresponding to the target address and to the transaction type by initiating the subsequent access at the expiration of the latency period.

Address dependent retry system to program the retry latency of an

A predictive arbitration system for interfacing a plurality of peripheral component interconnect (PCI) agents coupled to a first PCI bus with a second PCI bus. In one embodiment, the present predictive arbitration system includes a first PCI bus adapted to transmit data signals. A plurality of PCI agents are coupled to the first PCI bus. A predictive arbiter is coupled to both the first PCI bus and a second PCI bus. The predictive arbiter is also coupled to the plurality of PCI agents. The predictive arbiter is configured to receive requests for access to the first or second PCI bus from any of the plurality of PCI agents. The predictive arbiter, upon receiving requests for access, transmits one of the requests to a second arbiter coupled to the second PCI bus, wherein the selected and transmitted request originates from a selected one of the plurality of PCI agents. The predictive arbiter is also adapted to receive a grant signal from the second arbiter in response to the selected and transmitted request. The predictive arbiter further comprises a predictive arbitration system for enabling a grant line coupled to the selected one of the plurality of PCI agents before the grant signal is received from the second arbiter.

Predictive arbitration system for PCI bus agents

An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.

Combined consective byte update buffer

A system and method for determining which of plurality of peripheral components will have access to a peripheral component interconnect (PCI) bus when none of the plurality of peripheral components is currently requesting access to the PCI bus. In one embodiment a history buffer records all requests by a plurality of peripheral components for access to the PCI bus. The present invention then determines which of the plurality of peripheral components requests access to the PCI bus most often. Next, the present invention grants the peripheral component which requests access to the PCI bus most often access to the PCI bus when no other peripheral component is requesting access to the PCI bus. In so doing, the present invention 'parks' the PCI bus on the peripheral component which has, in the past, requested access to the PCI bus most often.

Adaptive arbitration mechanism for a shared multi-master bus

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis, maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on a time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache having various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occurs, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.

Coherent cache structures and methods

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.

Growing community of inventors

Phoenix, AZ, United States of America

Gabriel R Munguia