Altera Corporation

Gabriel Quan

Terry Borer

Stephen D Brown

Deshanand Pratap Singh

Chris Sanford

David Karchmer

Andrew Leaver

Vaughn Betz

Ryan Fung

Valavan Manohararajah

Ketan Padalia

Jordan Swartz

Scott James Brissenden

Caroline Pantofaru

Junaid Asim Khan

Kevin Chan

Ivan Hamer

Ian Chesal

Paul McHardy

Karl Schabas

Bruce B Pedersen

David Samuel Goldman

Jason Govig

Yuen Ho Choi

A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the design by reading the computer-readable list of the physical optimizations and applying the subset to a computer-readable description of the second version of the design.

Method and apparatus for performing fast incremental physical design optimization

A method for designing a system on a target device includes generating a first netlist for a first version of the system after performing synthesis in a first compilation. Optimizations are performed on the first version of the system during placement and routing in the first compilation resulting in a second netlist. A third netlist is generated for a second version of the system after performing synthesis in a second compilation. A hybrid netlist is generated from the first, second, and third netlists. Incremental placement and routing are performed on portions of the hybrid netlist that are new to the first compilation.

A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

Method and apparatus for performing compilation using multiple design flows

M/A for performing incremental compilation using top-down and bottom-up design approaches

A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.

Specifying placement and routing constraints for security and redundancy

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.

Method and apparatus for performing layout-driven optimizations on field programmable gate arrays

A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.

Method and apparatus for performing incremental compilation

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.

Method and apparatus for performing retiming on field programmable gate arrays

A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.

Method and apparatus for performing logic replication in field programmable gate arrays

Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices

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Toronto, Canada

Gabriel Quan