Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Weebit Nano Ltd.

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique

Université Joseph Fourier

Altis Semiconductor

Gabriel Molas

Amir Regev

Elisa Vianello

Jean-François Nodin

Guiseppe Piccolboni

Alessandro Bricalli

Sami Oukassi

Thierry Baron

Anthonin Verdy

Philippe Blaise

Faiz Dahmani

Paola Trotti

Michel Harrand

Gaël Pillonnet

Karim Aissou

Daeseok Lee

Gaël Castellan

Olivier Thomas

Thomas Ernst

Julien Buckley

Barbara De Salvo

François Rummens

Thomas Magis

Giorgio Palma

Khalil El Hajjam

Rémy Gassiloud

Rémy Gassilloud

Cécile Nail

Yifat Cohen

Marinela Barci

Jean-Baptiste Dory

Jérémy Guy

Gilbert Sassine

Stephane Becu

Marc Gely

Giuseppe Piccolboni

Gaël Castellani

Stéphanel Becu

Joël Minguet Lopez

A method for manufacturing an OxRAM resistive memory cell, includes forming a TiN lower electrode, firstly implanting Si atoms into the lower electrode with a first implantation dose and a first implantation acceleration voltage, the first implantation dose being strictly positive and strictly lower than 0.7·10cm, secondly implanting Si atoms into the lower electrode with a second implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, the second implantation dose being strictly positive and strictly lower than 0.6·10cm, the first and second acceleration voltages being selected to have an implantation profile following the first and second implantations having a maximum Si concentration at a depth of between 1 and 3 nm from the upper surface of the lower electrode, depositing an active layer onto the lower electrode implanted, depositing an upper electrode onto the active layer.

Method for manufacturing an OxRAM-type resistive memory cell and associated OxRAM-type memory cell

A memory includes at least one resistive memory cell and a write device. The memory cell includes a memory element having at least a highly resistive state and a lowly resistive state, and a selector arranged in series with the memory element, the selector being electrically conductive when a voltage greater than a given threshold voltage is applied to the selector. The write device includes at least one write capacitor and one charging device, and is configured to charge the write capacitor and then to connect it to the memory cell to program that cell.

Resistive memory with selector, equipped with a write capacitor, and associated writing method

An OxRAM resistive memory cell includes a lower electrode, an upper electrode, and an active layer which extends between the lower electrode and the upper electrode. The active layer includes a layer of a first electrically insulating oxide, wherein an electrically conductive filament can be formed, then subsequently broken and reformed several times successively. The upper electrode includes a reservoir layer, capable of receiving oxygen, which includes an upper part made of a metal and a lower part made of a second oxide, the second oxide being an oxide of the metal and including a proportion of oxygen such that the second oxide is electrically conductive.

Low forming voltage OxRAM memory cell, and associated method of manufacture

A method for manufacturing an OxRAM type resistive memory cell including a silicon oxide layer, the method including determining manufacturing parameter values enabling the resistive memory cell to have an initial resistance between 10Ω and 3·10Ω; and forming on a substrate a stack successively including a first electrode, the silicon oxide layer and a second electrode, by applying the manufacturing parameter values.

Method for manufacturing an OxRAM type resistive memory cell

A method for determining a value of a manufacturing parameter of a resistive memory cell, the resistive memory cell including a stack of layers, includes providing reference memory cells corresponding to technological alternatives of the stack of layers; measuring for each reference memory cell an initial resistance value; determining for each reference memory cell a programming parameter value selected from among the resistance in a high resistance state and the programming window; establishing a relationship between the programming parameter and the initial resistance from the initial resistance values and the programming parameter values; and determining the manufacturing parameter value for which the programming parameter is greater than or equal to a target value, from the relationship between the programming parameter and the initial resistance and from a dependency relationship between the initial resistance and the manufacturing parameter.

Method for determining a manufacturing parameter of a resistive random access memory cell

A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N−1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j−1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j−1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.

Method for resetting an array of resistive memory cells

A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

Method for programming an array of resistive memory cells

A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.

Memory comprising a matrix of resistive memory cells, and associated method of interfacing

A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N−1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.

A memory comprising: a resistive-switching element having first and second electrodes separated by a layer of insulator; an energy storage component or load coupled to the resistive-switching element via a first switch; and a control circuit configured: to program the resistive-switching element to have a set state, wherein, in the set state, a filament forms a conducting path between the first and second electrodes; and, following a dissolution of the filament, to recover electrical energy, generated by the dissolution of the filament, from one of the first and second electrodes by activating the first switch.

Energy recovery in filamentary resistive memories

A three dimensional memory includes flat electrodes, each defining a plane; a vertical electrode, extending essentially along an axis perpendicular to the plane defined by each flat electrode; floating electrodes, each situated between a flat electrode and the vertical electrode; first layers of an insulating material, each flat electrode being separated from the preceding and/or following flat electrode by a first layer of an insulating material; first layers of a first active material, each layer of an active material separating a flat electrode from the floating electrode that is associated therewith; a second layer of a second active material separating the vertical electrode from the floating electrodes. The first active material forms a selector or a memory point and the second active material forms a memory point or a selector. Each flat electrode includes first, second and third sub-layers made of, respectively, first, second and third conductive materials.

Three dimensional resistive random access memory and method enabling such a memory to be obtained

A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.

Resistive random access memory device

A solution for using elementary electrochemical components, manufactured from the same arrangement of materials and incorporated in a single electronic circuit, for information storage or for energy storage, is presented. Electrochemical components incorporating a first electrode, a second electrode and an active area between the two, can, by the application of different voltages for switching from a highly resistive state to a weakly resistive state or for switching from a state having one given electromotive force to a state having another electromotive force, be used respectively as a memory or as a battery.

Method for using electrochemical components for storage of energy and information and associated electronic circuit

A method for programming a resistive random access memory including a matrix of memory cells. This method includes a programming procedure that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix, the programming voltage ramp starting at a first non-zero voltage value, called start voltage, and ending at a second voltage value, called stop voltage, greater in absolute value than the first voltage value. The stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage (V), N being the number of memory cells in the at least one part of the matrix.

Method for programming a resistive random access memory

A semiconductor component includes a first electrode, designated flat electrode, defining a plane; a second electrode, designated active electrode, separated from the first electrode by an electrolyte layer; a pillar, designated vertical pillar, extending essentially along an axis perpendicular to the plane defined by the flat electrode, the pillar including a third electrode, designated vertical electrode and an information storage layer, the information storage layer covering a surface of the vertical electrode; the flat electrode and the vertical pillar being laid out so as to form a memory point. In addition, the materials of the active electrode and the electrolyte layer are chosen so as to form an energy storage zone with the flat electrode.

Growing community of inventors

Grenoble, France

Gabriel Molas