International Business Machines Corporation

Gabriel M Silberman

Vijay Sourirajan Iyengar

Barry Kumin Rosen

Zeev Barzilai

Zeev Barazilai

A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.

Method for the modeling and fault simulation of complementary metal

A method of simulating a differential cascode voltage switch circuit (domino circuit) by replacing each switch-level logic tree by a three-section Boolean tree. In each section, a switch is replaced by an AND gate. The first and third section pass signals in one direction and the second section passes signals in the opposite directions. The three sections are interconnected end to end. Various faults can be simulated by holding selected internal signals at faulty values.

Fault simulation for differential cascode voltage switches

A shift register latch (SRL) arrangement for testing a combinational logic circuit, producing true and complement outputs in nature, has two clocked DC latches and additional circuitry for providing an input to the second latch. Clock signal trains and an extra TEST signal are used to control the SRL arrangement in different modes. In a first mode, one of the outputs from the combinational logic circuit is latched into the first latch and provided to a succeeding combinational logic circuit. In a second mode, a plurality of the SRL arrangements are interconnected together to form a shift register chain so that each latch acts as one position of the shift register chain. Further, in a third mode, the true and complement outputs of the combinational logic circuit are exclusive ORed and its result is latched into the second latch. During the third mode, output of the first latch is prevented from being latched into the second latch.

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Haifa, Israel

Gabriel M Silberman