Psiquantum Corp.

Gabriel J Mendoza

Ramakanth Alapati

Albert Wang

John Eugene Berg

Matteo Staffaroni

Mark G Thompson

Soumyadipta Basu

Bradley Snyder

Faraz Najafi

Vimal Kumar Kamineni

Wenguang Li

Khanh Tran

David Schiff

Takashi Orimoto

Alain Shang

Luu Nguyen

Himani Kamineni

A device includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die bonded to the PIC die. The PIC die includes a waveguide layer including a waveguide and a grating coupler configured to couple incident light into the waveguide, and a first set of dielectric layers on the waveguide layer. The EIC die includes a semiconductor substrate and a second set of dielectric layers on the semiconductor substrate. The first set of dielectric layers faces the second set of dielectric layers. The PIC die and the EIC die include a trench aligned with the grating coupler, the trench extending through the semiconductor substrate, the second set of dielectric layers, and the first set of dielectric layers to the waveguide layer such that the incident light may pass through the trench to reach the grating coupler. A multi-step dry etching process is used to form the trench.

Structure and method to remove semiconductor chip material for optical signal access to a photonic chip

An optical interposer can be formed from multiple wafers, including a photonic integrated circuit wafer and an interposer wafer. The photonic integrated circuit wafer can be bonded to a rigid carrier structure, and material near waveguides can be removed such that the waveguides can be coupled to waveguides of the interposer. The photonic integrated circuit can be separated into multiple rigid dies which can be bonded to the interposer separately. Additional processing can be performed to form electrical connections to the rigid dies to form an ultra-low optical interposer.

Low loss optical interposer

A modular distributed cryogenic distribution system, comprising: a common chamber housing cryogenic fluid conduits; and a plurality of cryochambers connected to the common chamber. A method of operating a modular distributed cryogenic distribution system comprising a common chamber housing cryogenic fluid conduits, and plural cryochambers connected to the common chamber, includes raising one the plurality of cryochambers room temperature while a second one of the plurality of cryochambers operates at a cryogenic temperature.

Modular distributed cryogenic system

A system includes a plurality of wafer-scale modules and a plurality of optical fibers. Each wafer-scale module includes an optical backplane and one or more die stacks on the optical backplane. The optical backplane includes a substrate and at least one optical waveguide layer configured to transport and/or manipulate photonic quantum systems (e.g., photons, qubits, qudits, large entangled states, etc.). Each die stack of the one or more die stacks includes a photonic integrated circuit (PIC) die optically coupled to the at least one optical waveguide layer of the optical backplane. The plurality of optical fibers is coupled to the optical backplanes of the plurality of wafer-scale modules to provide inter-module and/or intra-module interconnects for the photonic quantum systems.

Multi-chip photonic quantum computer assembly with optical backplane interposer

A device includes a die stack including a first die including a quantum circuit and a second die including an electronic circuit. The second die and the first die face each other. A coupler is bonded to a first surface of the first die, an optical fiber is coupled to the coupler for coupling light from the optical fiber to the quantum circuit.

Photonic quantum computer assembly with a quantum computing die facing an electronic circuit die

An assembly system for assembling an optical die to an optical substrate includes test equipment configured to test optical couplers formed between the optical die and the optical substrate. The assembly system is configured to adjust an alignment of the optical die relative to the optical substrate until the optical couplers meet a performance metric. After the performance metric is met the optical die is permanently attached to the optical substrate.

Active alignment of optical die to optical substrates

Techniques disclosed herein relate generally to integrating photonic integrated circuits and electronic integrated circuits in a same package. A device includes a semiconductor substrate and a die stack on the semiconductor substrate. The die stack includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die. The PIC die includes a PIC substrate and a photonic integrated circuit formed on the PIC substrate. The EIC die includes an EIC substrate and an electronic integrated circuit formed on the EIC substrate. The EIC die and the PIC die are bonded such that the PIC substrate and the EIC substrate are disposed on opposing sides of the die stack. The PIC substrate is bonded to the semiconductor substrate. The device also includes a cooling plate bonded to the EIC substrate.

Hybrid system including photonic and electronic integrated circuits and cooling plate

A system includes a first photonic integrated circuit. The circuit includes a qubit encoder configured to receive a spatial-mode qubit and convert the spatial-mode qubit to a temporal-mode qubit and an optical interconnect configured to receive and transmit the temporal-mode qubit. The system further includes a second photonic integrated circuit, itself including a qubit decoder configured to receive the temporal-mode qubit and convert the temporal-mode qubit back into the spatial-mode qubit.

Time-bin qubit converter

A device includes a die stack including a first die including a quantum circuit and a second die including an electronic circuit. The second die and the first die face each other. The device also includes a first interconnect between the quantum circuit and the electronic circuit and a second interconnect between the quantum circuit and the electronic circuit.

Photonic quantum computer assembly

Techniques disclosed herein relate to devices that each include one or more photonic integrated circuits and/or one or more electronic integrated circuits. In one embodiment, a device includes a silicon substrate, a die stack bonded (e.g., fusion-bonded) on the silicon substrate, and a printed circuit board (PCB) bonded on the silicon substrate, where the PCB is electrically coupled to the die stack. The die stack includes a photonic integrated circuit (PIC) that includes a photonic integrated circuit, and an electronic integrated circuit (EIC) die that includes an electronic integrated circuit, where the EIC die and the PIC die are bonded face-to-face (e.g., by fusion bonding or hybrid bonding) such that the photonic integrated circuit and the electronic integrated circuit face each other. In some embodiments, the device also includes a plurality of optical fibers coupled to the photonic integrated circuit.

Growing community of inventors

San Francisco, CA, United States of America

Gabriel J Mendoza