Advanced Micro Devices Corporation

Microsoft Technology Licensing, LLC

Ati Technologies Ulc

Advance Micro Devices, Inc.

Advanced Micro Device, Inc.

Gabriel H Loh

James Michael O'Connor

Yasuko Eckert

Nuwan S Jayasena

Michael Ignatowski

Bradford Michael Beckmann

Michael J Schulte

Lisa R Hsu

Mithuna Shamabhat Thottethodi

Mauricio Breternitz, Jr

Mark Henry Oskin

Jaewoong Sim

Sergey Blagodurov

William Louie Walker

Mitesh Ramesh Meswani

John Kalamatianos

Rahul Kumar Agarwal

Vilas K Sridharan

Srilatha Manne

Arkaprava Basu

Onur Kayiran

Michael Warren Boyer

Matthew R Poremba

Douglas Christopher Burger

David Andrew Roberts

Mark Richard Nutter

Karin Strauss

Mark Donald Hill

Jay E Fleischman

Marko Scrbak

Niladrish Chatterjee

Akhil Arunkumar

John Robert Slice

David S Christie

Milind S Bhagavat

Maurice B Steinman

Andrew Gregory Kegel

Paul J Moyer

Kevin John McGrath

Jagadish B Kotra

Manish Arora

Ganesh Suryanarayan Dasika

Raja Swaminathan

Timothy Sherwood

Angela Beth Dalton

Eric H Van Tassell

Valentina Salapura

Michael Mantor

James Raymond Magro

Yi Xu

Maxim V Kazakov

Joseph Lee Greathouse

Sudhanva Gurumurthi

Jaewoong Chung

Brett P Wilkerson

Anthony T Gutierrez

Eric Christopher Morton

Jimshed B Mirza

Michael Estlick

Tarun Nakra

Steven E Raasch

Seyedmohammad SeyedzadehDelcheh

Alan Dodson Smith

Stuart Schechter

Shuai Che

Vedula Venkata Srikant Bharadwaj

Amin Farmahini-Farahani

Gabriel Wong

Niti Madan

Rahul Agarwal

Abhinav Vishnu

Michael S Alfano

Derek R Hower

Mohamed Assem Ibrahim

Derrick Allen Aguren

Georgios Mappouras

Salonik Resch

Syed Ali Jafri

Amro Awad

Prashant Jayaprakash Nair

Weon Taek Na

Guilherme Cox

Thiruvengadam Vijayaraghavan

Gautam Tarasingh Hazari

Andreas Prodromou

Todd David Basso

Vadim Vadimovich Nikiforov

Alexander Toufic Freij

Syed Ali R Jafri

Hye Ran Jeon

Kai K Chang

Rachata Ausavarungnirun

Subho Chatterjee

Kevin J Mcgrath

Cache replacement policies are described. In accordance with the described techniques, a request for data is received and a cache replacement policy controls how a controller responds to the request. The cache replacement policy assigns each cacheline a priority value, which indicates whether the cacheline should be preserved relative to other cachelines, in response to the request being a cache miss that necessitates eviction of at least one cacheline. The cache replacement policy decrements priority values until at least one cacheline achieves a minimum priority value, at which point a cacheline is evicted. The cache replacement policy designates certain cachelines as protected, either via a separate protected indicator or via the cacheline's priority value, which causes unprotected cachelines to be selected for eviction while favoring preservation of protected cachelines in the cache.

Super-temporal cache replacement policy

An electronic device includes processing circuitry that executes a lookup table (LUT) vector instruction. Executing the lookup table vector instruction causes the processing circuitry to acquire a set of reference values by using each input value from an input vector as an index to acquire a reference value from a reference vector. The processing circuitry then provides the set of reference values for one or more subsequent operations. The processing circuitry can also use the set of reference values for controlling vector elements from among a set of vector elements for which a vector operation is performed.

Lookup table (LUT) vector instruction

The disclosed device uses a control circuit configured to (i) receive branch misprediction information corresponding to a mispredicted branch window of instructions and (ii) send a misprediction status of a memory access from the mispredicted branch window of instructions, and a cache prefetcher of a cache configured to train using a set of memory accesses that are updated in response to receiving the misprediction status from the control circuit.

Systems and methods for branch misprediction aware cache prefetcher training

An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.

Systems, methods, and devices for advanced memory technology

A method for performing prefetching operations is disclosed. The method includes storing a recorded access pattern indicating a set of accesses for a region; in response to an access within the region, fetching the recorded access pattern; and performing prefetching based on the access pattern.

Region pattern-matching hardware prefetcher

A data processing node includes a processor element and a data fabric circuit. The data fabric circuit is coupled to the processor element and to a local memory element and includes a crossbar switch. The data fabric circuit is operable to bypass the crossbar switch for memory access requests between the processor element and the local memory element.

Locality-based data processing

The disclosed semiconductor package includes a first chiplet area for receiving a first chiplet, a second chiplet area for receiving a second chiplet, and a host die coupled to the first and second chiplet areas. The semiconductor package also includes an interconnect directly coupling the first chiplet area to the second chiplet area. Various other methods, systems, and computer-readable media are also disclosed.

Backside interface for chiplet architecture mixing

An approach is provided for implementing register based single instruction, multiple data (SIMD) lookup table operations. According to the approach, an instruction set architecture (ISA) can support one or more SIMD instructions that enable vectors or multiple values in source data registers to be processed in parallel using a lookup table or truth table stored in one or more function registers. The SIMD instructions can be flexibly configured to support functions with inputs and outputs of various sizes and data formats. Various approaches are also described for supporting very large lookup tables that span multiple registers.

Register based SIMD lookup table operations

An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

Flexible, scalable graph-processing accelerator

The disclosed device a controller that sets an iteration counter for a loop based on an iteration value read from a loop iteration instruction for the loop. The controller also updates the iteration counter based on a number of times a loop heading instruction for the loop is decoded. When the iteration counter reaches an end value, the controller selects a not taken identifier for the loop to be fetched, to avoid a branch misprediction. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for programmed branch predictors

A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

3D semiconductor package with die-mounted voltage regulator

A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for throttling prefetchers to prevent training on irregular memory accesses

Systems and methods are disclosed that map quantum circuits to physical qubits of a quantum computer. Techniques are disclosed to generate a graph that characterizes the physical qubits of the quantum computer and to compute the resource requirements of each circuit of the quantum circuits. For each circuit, the graph is searched for a subgraph that matches the resource requirements of the circuit, based on a density matrix. Physical qubits, defined by the matching subgraph, are then allocated to the logical qubits of the circuit.

Quantum circuit mapping for multi-programmed quantum computers

In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.

Re-fetching data for L3 cache data evictions into a last-level cache

Growing community of inventors

Bellevue, WA, United States of America

Gabriel H Loh