Infineon Technologies Ag

Gabriel-Dumitru Cretu

Christian Cornelius Russ

Filippo Magrini

Eric Pihet

Andreas Rupp

Bernhard Stein

Michael Ammer

An ESD protection circuit includes a silicon controlled rectifier (SCR) including a first conduction path between a first node and a second node and a clamp circuit coupled to a control terminal of the SCR. The clamp circuit is part of a second conduction path between the first node and the second node. During an ESD event, the clamp circuit conduct an ESD current until a threshold IV point is reached. The clamp circuit triggers the SCR, which then acts as a snapback device to conduct the ESD current at a lower voltage.

ESD protection circuit

A silicon-controlled rectifier includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.

Silicon controlled rectifier

A clamping circuit for protection against ESD events is described. In accordance with one exemplary embodiment, the circuit comprises the following: a first transistor having a control terminal and a load current path connected between a first contact and a second contact; an amplifier circuit having an amplifier input and an amplifier output connected to the control terminal of the transistor; and a trigger circuit, which is connected between the first contact and the second contact, and comprises a second transistor. The trigger circuit is configured to generate a voltage swing at the amplifier input as a reaction to a discharge current at the first contact by virtue of the fact that at least part of the discharge current drives a control terminal of the second transistor via an intrinsic capacitance of the second transistor.

Semiconductor switch with ESD protection circuit

A silicon-controlled rectifier (SCR) includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.

A silicon-controlled rectifier (SCR) includes a semiconductor body including a first main surface and an active device region. First through fourth surface contact areas at the first main surface are arranged directly one after another along a lateral direction. The semiconductor body is electrically contacted at each surface contact area. First and third SCR regions of a first conductivity type directly adjoin the first and third surface contact areas, respectively. Second and fourth SCR regions of a second conductivity type directly adjoin the second and fourth surface contact areas, respectively. The second SCR region at least partially overlaps a first well region of the first conductivity type at the first main surface. The first SCR region at most partially overlaps the first well region at the first main surface, and is electrically connected to the second SCR region. The third SCR region is electrically connected to the fourth SCR region.

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Munich, Germany

Gabriel-Dumitru Cretu