Motorola Corporation

Gabriel Bracha

Ilan Algor

Eytan Weisberger

Yehuda Volpert

Eytan Weissberger

In laying out electonic devices on a substrate the routing of nets is important in minimizing conductor area and improving performance. A method for routing of nets in an electonic device which has a plurality of clusters is disclosed which separates the intra cluster routing and the channel routing between the clusters. For the intra cluster routing a topological graph is proposed to be used for mapping a subgraph which is representative of the nodes in a net belonging to a cluster to be routed.

Method for routing of nets in an electronic device

In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.

Method for testing and for generating a mapping for an electronic device

A method for forming one or more redundant vias (38a-38x) around a critical via (36) involves providing an integrated circuit design file (12) containing several overlay layers. Critical vias in the file (12) are identified via a step (16). Several redundant vias are serially placed around and connected in parallel to the critical via (36), and design rules are checked for each redundant via by performing steps (24-30). Redundant vias which do not violate design rules (26) are kept in a separate redundant overlay layer and added to the design of the integrated circuit. The added redundant vias increase the yield of the integrated circuit by bolstering the integrity of critical via connections.

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Tel Aviv, Israel

Gabriel Bracha