Xilinx, Inc.

Gabor Szedo

Hemang Parekh

Wilson Chung

L James Hwang

Jeffrey Stroomer

Sean Kelly

Hai-Jo Tarn

Jeffrey Allan Graham

Elizabeth R Cowie

Singh Vinay Jitendra

Ted Nelson Booth

Peter Szántó

Béla Fehér

Helen Hai-Jo Tarn

Steven P Elzinga

Vanessa Y Chou

Christopher J Martin

Vanessa Yu-Mei Chou

A method relating generally to image processing is disclosed. In such a method, an image is preprocessed for noise suppression and edge detection with filters. The image is hierarchically decomposed to provide an image pyramid. The hierarchical decomposition includes successively down-scaling the image to provide different resolutions of the image corresponding to levels of the image pyramid. The image and the different resolutions of the image provide a set of images. A scene analysis of the set of images is performed. The performing of the scene analysis includes determining qualifications of blocks of the set of images for feature tracking. A subset of the blocks determined to be qualified for the feature tracking is selected. Motion estimation is performed on the subset of the blocks. The motion estimation is performed using a hierarchical set of motion estimation engines corresponding to levels of the image pyramid.

Image stabilization

A circuit for generating a digital image is described. The circuit comprises an image capture circuit; an edge mapping circuit coupled to the image capture circuit, the edge mapping circuit generating a mapping of edges in the image; and an edge enhancement circuit coupled to the edge mapping circuit. The edge enhancement circuit modifies aberrations in the image which are associated with an edge based upon a coefficient of a plurality of directional coefficients associated with an edge. A method of generating a digital image is also described.

Circuits for and methods of generating a digital image

A method of generating a digital image is described. The method comprises detecting light from a scene to form an image; identifying an aberration in the image; and implementing a color filter array interpolator based upon the detected aberration in the image. A device for generating a digital image is also described.

Method and device for generating a digital image based upon a selected set of chrominance groups

Circuits, systems, and methods for processing outlier pixels include a spatial filter and a temporal filter. The spatial filter is configured to compute a pixel difference for each pixel as a function of a pixel value of the pixel and pixel values of nearby pixels within each frame. The spatial filter is configured to dynamically add the pixel to a candidate list when the pixel difference exceeds a threshold value. The temporal filter dynamically removes a pixel from the candidate list when there is a divergence of a pixel value of the pixel in successive frames. The temporal filter determines a pixel in the candidate list is an outlier pixel when there is no such divergence in the successive frames.

Determining outlier pixels of successive frames

A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.

Scalable architecture for rank order filtering

A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.

Data reorganizer for fourier transformation of parallel data streams

Weight normalization in hardware or software without a division operator is described, using only right bit shift, addition and subtraction operations. A right bit shift is performed on an expected sum to effectively divide the expected sum by two to provide a first updated value for the expected sum. An iteration is performed which includes: incrementing with a first adder a first variable by the first updated value of the expected sum to provide an updated value for the first variable; subtracting with a first subtractor a second weight from a first weight to provide a first updated value for the first weight; and performing a left bit shift on the second weight to effectively multiply the second weight by two to provide a first updated value for the second weight.

Weight normalization in hardware without a division operator

In one embodiment of the present invention, a method for determining a phase alignment of a Bayer color filter array is provided. A quincunx lattice of the color filter array corresponding to a first color component is determined from an input frame of image data. Elements of the color filter array corresponding to first and second rectangular lattices of the color filter array are selected. Second and third color components corresponding to elements of the first and second rectangular lattices are determined from the sample values in an input frame of image data.

Color filter array alignment detection

A method of reducing aberrations in a digital image comprises capturing input samples associated with a plurality of pixels arranged in a matrix, wherein each pixel is associated with a color defining the digital image; establishing vertical chrominance groups associated with columns of the matrix and horizontal chrominance groups associated with rows of the matrix; determining chrominance values for the chrominance groups; determining, for each chrominance group, a mean value and, a sum of absolute differences between the chrominance values and the mean value for the chrominance values of the chrominance group; calculating, by a signal processing device, a plurality of weights comprising vertical weights associated with the vertical chrominance groups and horizontal weights associated with the horizontal chrominance groups based upon the sums of absolute differences; and determining a missing color component for a predetermined pixel of the plurality of pixels using the plurality of weights.

Methods of reducing aberrations in a digital image

Approaches for assembling an electronic circuit design. A processor performs operations including instantiating and coupling a plurality of instances of functional blocks in the design, including at least one meta block instance. The plurality of instances of functional blocks are displayed as respective graphical objects and identifiers of two or more implementations for the meta block instance from a meta block library are displayed. In response to designer selection of one implementation from the meta block library, a specification of the selected one implementation for the meta block instance is stored in association with the design. In response to designer selection of a graphical object corresponding to the at least one meta block instance, a designer-editable version of the one implementation is displayed. An updated specification of the one implementation associated with design is stored in response to designer modification of the designer-editable version of the one implementation.

Interface for managing multiple implementations of a functional block of a circuit design

Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Quadratic approximation for fast fourier transformation

Generating a high-level, bit-accurate and cycle-accurate simulation model. The various embodiments generate the simulation model from a functional description of a module and an HDL description of the module. The functional description may be un-timed and specified in a high-level language. The HDL description is realizable in hardware. The simulation model is created by obtaining the control specification from the HDL description and combining the control specification with the data path description from functional description.

Generation of a high-level simulation model of an electronic system by combining an HDL control function translated to a high-level language and a separate high-level data path function

A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.

Method of and circuit for buffering data

Various approaches for performing a fast-Fourier transform (FFT) of N input data elements using a radix K decomposition of the FFT are disclosed (K&#x3e;=2, and N&#x3e;=8). In one approach, N/K input data elements are written to respective ones of K addressable memories, and N/K*logN passes are performed on the input data. Each pass includes reading K data elements in parallel from the K addressable memories using the respectively generated addresses, the K data elements being in a first order corresponding to the respective memories; permuting the first order of K data elements into a second order of K data elements; performing a radix K calculation on the second order of K data elements, resulting in corresponding result data elements in the second order; permuting the second order of K result data elements into the first order; and writing the K result data elements in parallel to the corresponding K addressable memories using the respective addresses.

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Longmont, CO, United States of America

Gabor Szedo