International Business Machines Corporation

Globalfoundries Inc.

Gabor J Dozsa

Joseph D Ratterman

Sameer Kumar

Philip Heidelberger

Burkhard Steinmacher-Burow

Brian E Smith

Michael A Blocksome

Robert William Wisniewski

Thomas M Gooding

Douglas R Miller

Amith R Mamidala

Michael K Gschwind

Valentina Salapura

Charles J Archer

Dong Chen

Paul William Coteus

Alan G Gara

Adam James Muff

Todd Edward Takken

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

John A Gunnels

Mark Edwin Giampapa

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

Thomas Winters Fox

John Kevin O'Brien

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

James Anthony Marcella

George L Chiu

Todd Alan Inglett

Krishnan Sugavanam

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Craig Brian Stunkel

Rudolf Adriaan Haring

David L Satterfield

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Ralph E Bellofatto

Peter Boyle

Brant L Knudson

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Gheorghe Almasi

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing, by that available core on the compute node, that next shared memory allreduce work unit.

Performing an allreduce operation using shared memory

A shared address space on a compute node stores data received from a network and data to transmit to the network. The shared address space includes an application buffer that can be directly operated upon by a plurality of processes, for instance, running on different cores on the compute node. A shared counter is used for one or more of signaling arrival of the data across the plurality of processes running on the compute node, signaling completion of an operation performed by one or more of the plurality of processes, obtaining reservation slots by one or more of the plurality of processes, or combinations thereof.

Shared address collectives using counter mechanisms

In an embodiment, a send thread receives an identifier that identifies a destination node and a pointer to data. The send thread creates a first send request in response to the receipt of the identifier and the data pointer. The send thread selects a selected channel from among a plurality of channels. The selected channel comprises a selected hand-off queue and an identification of a selected message unit. Each of the channels identifies a different message unit. The selected hand-off queue is randomly accessible. If the selected hand-off queue contains an available entry, the send thread adds the first send request to the selected hand-off queue. If the selected hand-off queue does not contain an available entry, the send thread removes a second send request from the selected hand-off queue and sends the second send request to the selected message unit.

Message passing with queues and channels

In an embodiment, a reception thread receives a source node identifier, a type, and a data pointer from an application and, in response, creates a receive request. If the source node identifier specifies a source node, the reception thread adds the receive request to a fast-post queue. If a message received from a network does not match a receive request on a posted queue, a polling thread adds a receive request that represents the message to an unexpected queue. If the fast-post queue contains the receive request, the polling thread removes the receive request from the fast-post queue. If the receive request that was removed from the fast-post queue does not match the receive request on the unexpected queue, the polling thread adds the receive request that was removed from the fast-post queue to the posted queue. The reception thread and the polling thread execute asynchronously from each other.

A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation, an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.

Mechanism to support generic collective communication across a variety of programming models

Growing community of inventors

Yorktown Heights, NY, United States of America

Gabor J Dozsa