Oregon State University

Analog Devices,inc.

Microchip Technology Inc.

Kepler Computing Inc.

State of Oregon

Gabor C Temes

Paul F Ferguson, Jr

Paul F Ferguson

Jose Silva

Xavier S Haurie

Manjunath Kareppagoudr

Jyotindra Shakya

Jyotindra R Shakya

Yunteng Huang

Emanuel Caceres

Janos Markus

Shao-Feng Shu

Described herein is a mismatch shaping technique applied in digital-to-analog converters (DACs) for high pass filtering mismatch related errors. The mismatch shaping scheme is based on a zero mean error encoding technique, which can be applied directly to binary coded signals, without the use for binary to thermometer decoding and element shuffling. In at least one example, an apparatus is provided which comprises a mismatch shaping circuitry to receive an N-bit binary input bits and to generate an (N+1)-bit digital output. In at least one example, the apparatus further comprises a digital-to-analog converter to receive the (N+1)-bit digital output and to generate an analog output, wherein the mismatch shaping circuitry is to encode the (N+1)-bit digital output to shape mismatch errors in the digital-to-analog converter.

Mismatch shaping apparatus and method for binary coded digital-to-analog converters

A slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to a switch capacitor circuit so that operational transconductance amplifier (OTA) does not need to provide high peak current. This eliminates slewing altogether and allows using OTAs with less static current for the same settling accuracy.

Slewing mitigation apparatus for switched capacitor circuit

A signal scaling circuit for accurately reducing the effective amplitude of an input signal by a rational factor N/M, where N and M are integers and N&#x3c;M, is disclosed. An input, reference, bias and output node as well as control circuitry are selectively coupled to M switched capacitor circuits such that N/M scaling may be achieved. Cooperation between the M switched capacitor circuits and the control circuitry divides the M switched capacitors circuits into subsets of N and M&#x2212;N switched capacitors, respectively. Each subset is then selectively coupled to an input, reference and/or bias signal to produce an output signal having as one of its components an N/M portion of the input signal. Error reduction in the scaled signal is achieved by shuffling the switched capacitor circuits populating each subset after selected time intervals.

Switched capacitor signal scaling circuit

Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals Indicative of the digital signals to a signal conditioning stage at an output data rate different the input data mute.

Method and apparatus for use in switched capacitor systems

A track-and-hold circuit that utilizes the negative of the input signal to improve tracking of the input signal during the track mode. By applying the negative of the input signal to an amplifier node to which the output signal is coupled, the output signal is forced to track the input signal in magnitude and polarity. Single-ended and fully differential embodiments of the circuit are disclosed, as well as embodiments using an operational amplifier and a cascode inverter amplifier. An improved switching scheme reduces delay in the transition from the hold mode to the track mode. A sample-and-hold circuit may be constructed from a pair of the track-and-hold circuits.

Track-and-hold circuit utilizing a negative of the input signal for

An oversampling D/A converter system achieves high linearity and low quantization error by using dual internal D/A converters: one with high linearity but high quantization error and the other with low linearity but low quantization error. A signal path in the system includes an L-bit quantizer for quantizing a digital input signal into an L-bit signal plus a quantization error and a D/A converter for converting the L-bit signal and quantization error into an analog signal. A correction path that parallels the signal path includes an M-bit quantizer, where M is greater than L, and an M-bit D/A converter. A signal generated by the correction path cancels the shaped quantization error of the signal generated by the signal path by adding the negative of the shaped quantization error to the signal of the signal path. The resulting analog signal is filtered by a low-pass analog filter to extract the analog equivalent of the digital input signal. Various arrangements of filter stages are also disclosed for constructing preferred implementations of the oversampling D/A converter.

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Corvallis, OR, United States of America

Gabor C Temes