Xerox Corporation

University of California

Hughes Aircraft Company

Rockwell International Corporation

Temes, Gabor C.

Gabor C Temes

Robert H Walden

Tanju Cataltepe

Kenneth W Martin

Derek T Cheung

Fong J Wang

A precision sigma-delta analog-to-digital converter disposed to operate at a sampling rate giving rise to a relatively low oversampling ratio is disclosed herein. The high-order sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal to a digital output sequence. The inventive converter (10) includes a first integrating network (14) for generating a first sampled analog signal (X.sub.1) in response to the analog input signal. A second integrating network (18) generates a second sampled analog signal (X.sub.2) in response to the first sampled analog signal (X.sub.1). A third integrating network (22) generates a third sampled analog signal (X.sub.3) in response to the second sampled analog signal (X.sub.2). The sigma-delta converter (10) of the present invention further includes an internal quantizer (24) for generating the digital output sequence in response to the third sampled analog signal. A feedback network (28, 30) supplies the first, second and integrating networks (14, 18 and 22) with an analog feedback signal generated in response to the digital output sequence.

High-order sigma-delta analog-to-digital converter

A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.

Multi-stage sigma-delta analog-to-digital converter

A pipelined digital to analog converter is disclosed which utilizes a series of three capacitor and switch sections to convert a three bit segment of a digital word into an analog voltage. For a ten bit digital word, three 3-capacitor sections would be required with an additional capacitor section. The voltage across the output, or last, capacitor is the analog voltage in direct relation to the input digital word. Each of the three capacitor sections works in relation to switched transistors to charge and discharge in a predetermined fashion said capacitors, in relation to the binary level of each of the three digits in the input digital word. The circuit operates from the least significant bit to the most significant bit, and converts the input digital word to an output analog voltage.

Pipelined digital-to-analog converter

A switched capacitor pseudo-N-path filter stage includes an analog integrator circuit having an input, an output, and a feedback capacitor connected between the input and the output. A plurality of storage capacitors are connected across the feedback capacitor and an input capacitor is provided. The feedback capacitor and storage capacitors form an analog random access memory. A switching circuit selectively connects the input capacitor across electrical ground and between an input signal and the input of the integrator circuit, and also selectively connects the feedback capacitor and the storage capacitors between electrical ground and the output of the integrator circuit. In this manner, the input signal is filtered as the input capacitor samples the input signal and the charge on the input capacitor is circulated through the feedback capacitor and the storage capacitors.

Switched-capacitor pseudo-n-path filter

A solid state imager wherein a pixel non-uniformity correction system compensates for photosite non-uniformities by providing a linear correction method and utilizing three modes: mode #1--dark current detection, mode #2--uniform illumination, and mode #3--data detection mode. In the first calibration cycle, the outputs of all the photocells on an imager 10, representing 'dark current' are stored in an 'offset' memory 14. In the second calibration cycle, a uniform illumination from a constant light level is applied to the imager 10. This uniform illumination signal is passed to an arithmetic unit 18 where the dark current signal is subtracted from it and the difference is then stored in gain memory 28. The gain memory passes this signal back to the arithmetic unit 18, so that in the third mode, the data detection mode, the arithmetic unit 18 can electronically correct the data signals that were non-uniformly affected by the internal characteristics of the imager.

Pixel non-uniformity correction system

A switched capacitor type amplifier system including an operational amplifier is provided with compensating capacitive coupling during the non-sampling portion of the cycle from the output of the operational amplifier to its input, to avoid output discontinuities, and to provide compensation for the offset voltage of the operational amplifier. The circuit includes a two phase clock, with the signal input to the input capacitor being alternately sampled and blocked, and the capacitive compensation circuit mentioned above being alternately blocked and connected, respectively, during successive phases of the clock operation. Special circuitry for preventing 'clock feed-through' and for implementing a Multiplying Digital to Analog Converter, or MDAC, are disclosed.

Offset compensated switched capacitor circuits

An improved input circuit is provided for an array of photo detectors. For each photo detector in the array, the circuit utilizes a first FET with a source for coupling to an output of a photo detector, a gate coupled to a first gate voltage, and a drain for coupling to an output circuit. The first gate voltage is provided by a feedback circuit which utilizes matched properties of adjacent FETs. In one embodiment, FETs are used in an open loop feedback circuit to reduce the input impedance seen by the photodiode at the source of the first FET. A similar objective is accomplished in another embodiment utilizing FETs in a closed loop feedback circuit. Further embodiments utilize FETs arranged as a differential amplifier with active loads to provide a low input impedance and a virtual ground at the source of the first FET.

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Los Angeles, CA, United States of America

Gabor C Temes