Intel Corporation

Gabi Malka

Zeev Sperber

Tsvika Kurts

Ehud Cohen

Doron Orenstein

Ofer Levy

Guy Peled

Jason W Brandt

Itamar S Kazachinsky

Yael Shenhav

Gavril Margittai

Igor Yanover

Beeman C Strong

Gavri Berger

Omer Vikinski

Gilad Shmueli

Shmulik Branski

A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.

Method and apparatus for proactive throttling for improved power transitions in a processor core

In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

Using thresholds to gate timing packet generation in a tracing system

A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Real time instruction trace processors, methods, and systems

A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered. Thus, the invention maintains the consistency of received polygon state variables across parallel texture pipelines while simultaneously providing for efficient use of a multi-pipeline texture engine by triggering only one texture pipeline when a single texture operation is required.

Texture engine state variable synchronizer

An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

Texture engine memory access synchronizer

A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by evicting previously stored second data to a write back buffer. The at least one read request is then issued consecutively to system memory via the system memory bus. After issuance of the at least one read request, at least one write request is issued consecutively to send the second data in the write back buffer to the system memory via the system memory bus. The consecutive issuance of read and write requests avoids read-to-write and write-to-read bubbles that occur when alternating read and write requests are issued to system memory.

System and method for optimizing bus bandwidth utilization by grouping cache write-backs

A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.

Memory system for multiple data types

A graphics system is provided to implement compression of depth or z-data. The graphic system includes a buffer, a status table, and a read/write unit. The buffer stores depth data for multiple blocks of pixels in associated buffer entries. The status table stores status values for the entries of the buffer. The status value for a given entry indicates an access mode for the corresponding depth data according to whether the data is compressed, uncompressed or in a reference state. The read/write unit implements data accesses for a given entry responsive to the status value associated with the entry.

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Haifa, Israel

Gabi Malka