Mellanox Technologies, Ltd.

Gabi Liron

Liran Liss

Ariel Shahar

Ilan Pardo

Yuval Itkin

Miriam Menes

Aviad Shaul Yehezkel

Shahaf Shuler

Uria Basher

Yaniv Strassberg

Ahmad Atamli

Ran Avraham Koren

Guy Harel

Meni Orenbach

Moshe Shemesh

Chen Gonen

Apparatuses, systems, and techniques to detect a Denial of Service (DoS) attack on a target device by an entity. In at least one embodiment, the detection is followed by an event message to prevent the entity from sending further communications to the target device.

Protecting from denial of service attacks

The technology disclosed herein enables selective clearing of memory regions upon a context switch. An example method includes the operations of: receiving a memory access request referencing a memory region; determining an identifier of a current execution context associated with the memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, updating the metadata associated with the memory region to store the identifier of the current execution context; clearing at least a part of the memory region; and processing the memory access request with respect to the memory region.

Maintaining data confidentiality in shared computing environments

A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

Peripheral device with cache updating from multiple sources

A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.

Memory access tracking using a peripheral device

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Yokneam Illit, Israel

Gabi Liron