Hynix Semiconductor Inc.

Ga Won Lee

Jae Hoon Choi

Jae Chul Om

Sung Wook Park

Jae Hee Lee

The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes the insulating film spacer at a region where the plug is not formed to lower the aspect ratio between the metal lines, in a process of burying an insulating material between the metal lines to electrically insulate them. Therefore, the present invention can easily bury the insulating material even between the metal lines having a narrow gap without voids.

Method of forming inter-dielectric layer in semiconductor device

Provided is a method for manufacturing a semiconductor device including a plurality of different semiconductor elements with a transistor for fabricating the semiconductor device formed on a semiconductor substrate, an interlayer insulation film formed all over the upper part, and a hole trap site formed in the interlayer insulation film for preventing a mobile ion like H or moisture from penetrating, whereby it can be prevented that a leakage current increases abnormally where the voltage difference (Vgs) is lower than a threshold voltage.

Method for manufacturing semiconductor device

A method of forming a test pattern includes: forming first and second junction regions having a symmetrical structure on both side of field oxide layer formed on a semiconductor substrate; forming third and fourth junction regions having a asymmetrical structure on front and rear portions of the field oxide layer; forming a test pattern having first and second projection portions on the semiconductor substrate, in which both side portions of the test pattern are overlapped with the first and second junction regions and the first and second projection portions which are formed on front and rear portions of the test pattern are overlapped with the third and fourth junction regions; forming an inter insulating layer on a resulting structure after forming the test pattern; patterning the inter insulating layer to expose a portion of the first to fourth junction regions; forming current supply lines connected to the first and second junction regions, respectively; and forming voltage measuring lines connected to the third and fourth junction regions, respectively.

Method of forming a test pattern, method of measuring an etching characteristic using the same and a circuit for measuring the etching characteristic

The present invention relates to a method of manufacturing a thin film transistor in a semiconductor device. The present invention forms a single crystal silicon thin film on an interlayer insulating film on a single crystal driver transistor using a solid phase crystallization of amorphous silicon, forms a single crystal silicon thin film transistor (C&mdash;Si TFT) in the single crystal silicon thin film in order to uses it as a load transistor and uses a contact plug connecting a drain in the driver transistor and a drain in the load transistor as a SPC (solid phase crystallization) plug, in a process of depositing a silicon thin film on a single crystal transistor by a three-dimensional stack process to deposit to form a load transistor in a manufacture process of SRAM. Therefore, the present invention can improve the uniformity and reliability of the load transistor.

Growing community of inventors

Kyungki-do, South Korea

Ga Won Lee