Texas Instruments Corporation

G R Rao

Lionel S White, Jr

Joseph C McAlexander, Iii

Donald J Redwine

Jih-Chang Lien

Shyam Bhatia

John S Stanczak

David J McElroy

Chitranjan N Reddy

Gerald R Rogers

A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

High performance dynamic sense amplifier with voltage boost for row

An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.

Guard ring for reducing pattern sensitivity in MOS/LSI dynamic RAM

A dynamic read/write memory device using one-transistor N-channel silicon gate type cells is made by a double-level polysilicon process in which the field oxide is of reduced thickness for the cell array, and of conventional thickness for peripheral circuits. This reduces moat encroachment in the critical cell portion, yet does not force performance compromises in the critical speed paths.

Differing field oxide thicknesses in dynamic memory device

A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled drive transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

High performance dynamic sense amplifier voltage boost for row address

High performance dynamic sense amplifier with dual channel grounding

A processor system employs a self-refresh memory device which comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh address generator circuitry including an address counter or commutator and a multiplexer to insert the refresh address when a command is received or internally generated indicating a refresh cycle. If a refresh command is not being executed, the device is accessed by the processor in the usual manner if a memory address is received.

Processor system using on-chip refresh address generator for dynamic

A dynamic read/write memory device constructed in a semiconductor chip of the MOS VLSI type employs an on-chip substrate bias generator which is sequentially clocked by the clocks used in operation of the memory. The impact ionization current associated with each clock operation is thus individually supplied, and when a clock is not used the substrate bias for this clock is not generated.

Sequentially clocked substrate bias generator for dynamic memory

A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word address lines and the bias lines for the capacitors are formed by metal strips. The gates of the access transistors and the capacitor gates are polysilicon. Metal-to-polysilicon contacts are made to connect the metal word lines to the polysilicon gates of the access transistors and to connect the metal bias lines to the capacitor gates.

Method of making single-level polysilicon dynamic memory array

High performance dynamic sense amplifier with multiple column outputs

A dynamic read/write memory cell of the one-transistor N-channel silicon gate type is made by a double-level polysilicon process in which the implant dosage is reduced for the channel stop regions beneath the field oxide. This causes the signal level on the bit lines to be improved, and also reduces leakage problems.

Reduced field implant for dynamic memory cell array

A plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.

Method of making double level polysilicon series transistor devices

High performance dynamic sense amplifier with active loads

A semiconductor memory device of the single-chip MOS/LSI integrated circuit type has both serial access and random access arrays on the same chip. When the device is addressed, if the address is in the random access portion then data input or output is the same as in dynamic RAM operation, but if the address is in the serial arrays then access is different. For a read operation a row containing the addressed data is transfered serially from the serial access portion to a shift register coupled to the random access array, then this row of data is transfered into the columns of the array and output is accomplished in the usual manner. The random access or serial access arrays may be loaded serially.

Semiconductor integrated circuit memory device with both serial and

An MOS/LSI type dynamic RAM with single 5V supply and grounded substrate employs a pair of dummy columns on each end of the cell array to prevent pattern sensitivity in testing. The dummy columns have capacitors which alternate between large and small so a given cell will always read a '1' or '0' upon refresh. These cells are not accessed in normal read or write cycles. Thus, regardless of the row addressed, one column line half on each side will go high and the other low. This shields the ends of the array from diffusing electrons (minority carriers).

Dummy columns for reducing pattern sensitivity in MOS/LSI dynamic RAM

A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.

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Houston, TX, United States of America

G R Rao