Infineon Technologies Ag

Infineon Ag

Günter Gerstmeier

Michael Bernhard Sommer

Andreas Huber

A metallization surface (), which acts as an etching stop layer during the production of openings () in a passivation layer () applied to its upper face and protects an interconnect structure () arranged underneath it, is arranged in an uppermost metallization level (). A further opening is produced in the metal surface (), through which a focused ion beam is aimed at the interconnect structure () in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.

Semiconductor chip with metallization levels, and a method for formation in interconnect structures

An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.

Integrated semiconductor memory

An integrated circuit includes a voltage generator with a first controllable resistor and a second controllable resistor, through which a first input terminal that applies a first voltage potential and a second input terminal that applies a second voltage potential can be connected to an output terminal that generates an output voltage. In a manner dependent on the output voltage, a first comparator circuit generates a first control signal to control the first controllable resistor, and a second comparator circuit generates a second control signal to control the second controllable resistor. A control unit evaluates the control signals generated by the comparator circuits and drives the first and second controllable resistors of the voltage generator in such a way that in each case only one of the two controllable resistors has a low-resistance state.

Growing community of inventors

Hilg.-Tandern, Germany

Günter Gerstmeier