Nec Corporation

Nec Electronics Corporation

Renesas Electronics Corporation

Fuyuki Okamoto

Masayuki Mizuno

Yoshinori Muramatsu

Masayuki Furumiya

Hiroaki Ohkubo

Yoshihiro Nakagawa

Koichi Nose

Yoshio Kameda

A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Semiconductor device

From power supply potential wiring to ground potential wiring, a first inductor, a first resistance, a first output terminal, and a first transistor are series-connected in this order, and in parallel with these, a second inductor, a second resistor, a second output terminal, and a second transistor are series-connected in this order. And, one electrode of a first variable capacitor is connected between the first inductor and first resistor, and one electrode of a second variable capacitor is connected between the second inductor and second resistor. The other electrodes of the first variable capacitor and second variable capacitor are connected to a first frequency characteristics control terminal and a second frequency characteristics control terminal, respectively. In addition, drains of the first transistor and second transistors are connected to the first output terminal and second output terminal, respectively, sources of the same are connected to a drain of a third transistor, and gates of the same are connected to a first input terminal and a second input terminal, respectively. Furthermore, a gate of the third transistor is connected to a bias terminal, and a source of the same is connected to the ground potential wiring.

Frequency characteristics-variable amplifying circuit and semiconductor integrated circuit device

At the same control voltage Vtune, the oscillation frequency with only switches SWand SWbeing closed is higher than that with only switches SWand SWbeing closed. Accordingly, even when the oscillation frequency is lower than designed with only the switches SWand SWbeing closed and the capacitance of varactor diodes Dand Dcannot be controlled to provide the desired oscillation frequency, the desired oscillation frequency can be provided by closing only the switches SWand SWto control the capacitance of the varactor diodes Dand D. On the oscillation frequency, a coarse tuning can be performed by controlling the switches SWto SW, while a fine tuning can be performed with the varactor diodes Dand D. Consequently, the range of the oscillation frequency is increased.

Voltage controlled oscillator having switches to adjust effective inductor lengths

A solid-state imaging device has an array of pixels arranged in a matrix pattern of rows and columns. Each pixel has a photodiode for developing a voltage corresponding to light incident thereon, a first amplifying transistor for amplifying the voltage and a row select switching transistor responsive to a row select signal from a row line for coupling the amplified voltage to a column line. Multiple second amplifying transistors are respectively connected to multiple column lines. When the row select switching transistors of the pixels in one of the rows are turned on in response to a row select signal, the second amplifying transistors and the first amplifying transistors of the selected row jointly constitute voltage followers for respectively amplifying the voltages coupled to the column lines. Multiple column select switching transistors provide sequentially coupling of the outputs of the voltage followers to an output line in response to column select signals.

Solid-state imaging device with voltage followers formed by selected row transistors and column transistors

A hierarchical readout circuit includes a plurality of first capacitors for respectively interposed in a plurality of lines at which individual voltages are developed. Before the individual voltages appear at the lines, the inputs of the first capacitors are simultaneously biased at least once, and the outputs of the first capacitors are simultaneously biased. The output of each of the first capacitors is selectively biased again in the presence of the individual voltages at the lines. A plurality of buffers are connected in stages in a hierarchical configuration to the outputs of the first capacitors. Scanning circuitry selectively couples the output of a lower-stage buffer to a higher-stage buffer via a second capacitor. The output of the second capacitor is first biased before the individual voltages appear at the lines and then at periodic intervals before each first capacitor is selectively biased again.

Hierarchical pixel readout multiplexer with switched capacitors for cancelling buffer offsets

The solid state imaging device comprising active pixels has a structure in which transistors for amplification and which amplify an output signal of a photodiode composing a photoelectric conversion portion are constituted as a voltage follower. By using the transistors for amplification and having a voltage follower structure, a gain of amplifying a signal from each pixel is made unity, and an amplification gain can be larger than that of an amplification circuit having a conventional source follower structure. Thereby, noise immunity is improved. Also, by inserting switching transistors corresponding to row selecting transistors, circuit symmetry of a differential amplifier circuit can be improved.

Solid state imaging device having high output signal pain

There is provided a solid-state image sensor including (a) a plurality of pixels arranged in a matrix in a photoelectric transfer region, (b) at least one movement-detector located in the photoelectric transfer region, (c) a first Y-scanner making successive access to the pixels in rows in a predetermined region in the photoelectric transfer region, and (d) a first X-scanner reading out signals running through signal output lines extending through the predetermined region. The first and second scanners both scan a predetermined region associated with a movement-detector which has transmitted a detection signal. The solid-state image sensor makes it possible to immediately detect movement when it has occurred, identify a region in which movement has occurred, and detect movement while carrying out scanning in a normal mode.

Solid-state image sensor and method of driving the same

A photoreceiver circuit includes (a) a photoelectric conversion element for converting incident light to a current, (b) an analog voltage amplifier circuit for amplifying a voltage corresponding to the current of the photoelectric conversion element and for producing an amplified voltage as an output of the photoreceiver circuit, and (c) an analog multiplier circuit for multiplying the amplified voltage produced by the voltage amplifier circuit by an adjusting voltage and for producing an output current with a component proportional to a product of the amplified voltage and the adjusting voltage. The output current of the analog multiplier circuit is supplied to the photoelectric converter element, thereby forming a feedback path of the voltage amplifier circuit. A voltage-lowering part and a current-leaking part may be additionally provided. The voltage-lowering part is connected between the voltage amplifier and the analog multiplier circuit, and the current-leaking part is connected in parallel to the voltage-lowering part.

Gain-adjustable photoreceiver circuit with photoelectric converter and amplifier

A latch circuit with an NAND function comprises a three-input NAND gate circuit, a first transfer gate connected between a first input terminal and a first input of the NAND gate circuit, a second transfer gate connected between a second input terminal and a second input of the NAND gate circuit, and a third transfer gate connected between a third input terminal and a third input of the NAND gate circuit. An input of a feedback inverter is connected To an output of the NAND gate circuit, and an output of the feedback inverter is connected to the first input of the NAND gate circuit through a fourth transfer gate. The second and third inputs of the NAND gate circuit are pulled up to a logical high level through P-channel MOS transistors. The first, second, third and fourth transfer gates and the P-channel MOS transistors are controlled by a clock signal in such a manner that when the first, second and third transfer gates are on, the fourth transfer gate and the P-channel MOS transistors are off, so that the NAND gate circuit performs a NAND operation in response to input signals applied to the first, second and third input terminals, and when the first, second and third transfer gates are off, the third transfer gate and the P-channel MOS transistors are on, so that a latch operation is performed to maintain a logical value on the output of the NAND gate circuit.

Latch circuit having a logical operation function

A priority encoder for a normalization at a floating-point addition of subtraction for encoding a leading zero number of a difference of two input binary numbers within an error of -1, and a floating-point adder-subtractor using this priority encoder. The priority encoder includes a pre-encoder for outputting an n-bit bit string Q (=Q.sub.n, Q.sub.n-1, . . . and Q.sub.1,) from a combination (X.sub.i, Y.sub.i, X.sub.i-1, Y.sub.i-1) of ith and (i-1)th digits of input two binary numbers X and Y, and a conventional priority encoder circuit for encoding the bit string Q output from the pre-encoder. The floating-point adder-subtractor includes the priority encoder operating in parallel with a mantissa add-subtract circuit so as to output the leading zero number of the difference between the two binary numbers X and Y.

Priority encoder and floating-point adder-substractor

Apparatus for use in a floating-point and fixed-point adder-subtractor assembly. The apparatus includes a comparator and selector circuit disposed prior to an adder-subtracter for determining a larger and smaller operand prior to the addition and subtraction operation. The comparator and selector circuit inputs the larger operand into a first predetermined input of the adder-subtracter and the smaller operand into a second predetermined input of the adder-subtracter. Additionally, first and second selector circuits may be provided for multiplexing first and second fixed point data operands into the first and second inputs of the adder-subtracter, respectively. A shifter is provided for shifting at least one of the operands prior to inputting the operand into the adder-subtracter for selectively performing a position alignment. Accordingly, a simplified structure provides fixed-point and floating-point data addition-subtraction in a highly efficient manner.

Floating-point and fixed-point addition-subtraction assembly

In vector dividing the process employing convergence division method, the process steps are performed for performing pipeline processing of multiplying operation of the dividend and a first convergence factor in a speed of one clock cycle per one element to generate a first intermediate result vector data as a data before convergence, for performing pipeline processing of multiplying operation of the divisor and the first convergence factor in a speed of one clock cycle per one element to generate a second intermediate result vector data as a data before convergence, for storing the first and second intermediate result vector data to first and second intermediate result storing vector registers, respectively, for reading out of the first and second intermediate result vector data from the first and second intermediate result storing vector registers, respectively, per every clock cycles, for performing pipeline processing for multiplying operation of the read out intermediate result vector data and a second convergence factor as the next convergence factor in a speed of one clock cycle per one element to generate third and fourth intermediate result vector data, and for repeating the same process from the third step to fifth step until reaching to a nth convergence factor as a predetermined final convergence factor, and outputting a quotient vector as the final convergence result in a speed of one clock cycle per one element.

Vector division processing method and system

In a floating point arithmetic addition/subtraction system which is configured to receive a pair of input operands of floating point data including its mantissa part expressed in an absolute value so as to execute an addition/subtraction and which includes a mantissa adder, a normalizing shifter, an exponent part updater and a bit position decoder, integer data expressed in a 2's complement is supplied as one of the pair of input operands, and the integer data is converted into an absolute value by using the mantissa adder. Thereafter, the bit position of the obtained absolute value is modified by using the normalizing shifter so as to give a mantissa part, and a value of an exponent part is generated by using the updater and the bit position decoder.

Floating pointing arithmetic operation system

In an absolute value subtraction processing of .vertline.X-Y.vertline., carry generation and propagation functions and group carry generation and propagation functions are first generated. Then, a carry is calculated at the most significant bit in the summation of a first operand and a complement of '2' of a second operand by use of the above functions. Where the carry is '1', the above summation remains continued. Where the carry is zero, additional first and second functions are generated by inverting logic ORs of the carry generation and propagation functions and of the group carry generation and propagation functions. Thus, the summation of the second operand and a complement of '2' of the first operand is realized by use of the additional functions, the carry propagation function, and the group carry propagation function.

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Tokyo, Japan

Fuyuki Okamoto