Mitsubishi Denki Kabushiki Kaisha

Futoshi Tokunoh

Katsumi Satoh

Kazuhiro Morishita

Kazuhiko Niwayama

Kenji Oota

Tsutomu Nakagawa

Kouji Niinobu

Katsumi Sato

Tokumitsu Sakamoto

Shigekazu Yoshida

Koji Niinobu

Nozomu Sennenbara

Yasuo Tanaka

Kazuhisa Ide

Nobuhisa Nakasima

A gate electrode () is formed on the outer peripheral step portion (') of a semiconductor substrate () so as to face a pressure-contact supporting block (), and a convex contacting portion () is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (). The convex contacting portion () is formed of a convex portion integral with the gate electrode or formed of another gate electrode (&#x2032;).

Pressure-contact type semiconductor device

A compression bonded type semiconductor device including a semiconductor substrate having a gate electrode and a cathode electrode formed on a first surface and an anode electrode formed on a second surface opposite to the first surface, an external cathode electrode disposed so as to be compression bondable to the cathode electrode, and an external anode electrode disposed so as to be compression bondable the anode electrode. Also included is an insulating cylinder containing the semiconductor substrate, an external gate terminal having an outer peripheral portion protruding to an outside of the insulating cylinder and having a protrusion at an inner peripheral portion configured to about said gate electrode, and an elastic body configured to press the protrusion of the external gate terminal to the gate electrode.

Compression bonded type semiconductor device

Semiconductor device with a beveled and chamfered outer peripheral

A compression-type semiconductor device comprises a silicon substrate in which crystal orientation between main faces opposite to each other is not larger than &lt;1,0,0&gt; .+-.27.5.degree.; cathode and gate electrodes formed on one of the main faces of the silicon substrate; an anode electrode formed on the other of the main faces of the silicon substrate; a cathode thermal compensation plate for the cathode and gate electrodes; and an anode thermal compensation plate for the anode electrode.

Compression-type power semiconductor device

In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12). Thus, the turnon loss is reduced and the di/dt resistance is improved without deteriorating the withstand voltage and the ON-state resistance.

Gate turnoff thyristor with reduced gate trigger current

In a semiconductor device, a semiconductor element is stored in a casing while being held by external electrodes through first and second electrodes. The outer peripheral edge of the first electrode plate is projected outwardly beyond that of the semiconductor element and a ring-shaped groove is provided in the first surface of the first electrode plate along the outer peripheral edge of the semiconductor element such that a line, which is projected along the outer peripheral edge of the semiconductor element on the first surface of the first electrode plate, is located on the ring-shaped groove portion. The adhesive holding member is applied in the groove and the outer peripheral portion of the semiconductor element. Thus, the semiconductor element is fixed to the first electrode plate and is protected by the adhesive holding member which covers its end portion.

Process for adhesively attaching a semiconductor device to an electrode

A reverse conducting gate turn-off thyristor (RC-GTO) includes, in the same semiconductor body, a gate turn-off thyristor, a reverse current diode, and a semiconductor isolation region between the gate turn-off thyristor and the reverse current diode and having a first conductivity type semiconductor layer adjacent an anode electrode and spaced apart second conductivity type high-dopant-impurity-concentration regions opposite the anode electrode.

Reverse conducting gate turn-off thyristor

There is disclosed a semiconductor device wherein a p layer (7) is formed in an isolating portion (Z) and portions (1a, 1b) of an n-type base layer (1) lie on opposite sides of the p layer (7), the upper surfaces of the p layer (7) and the portions (1a, 1b) lying in the same plane as the upper surface of a p layer (3). The presence of the p layer (7) provides for high resistance to breakdown and high formation accuracy of the p layers (2, 3, 7) as compared with a structure in which the isolating portion (Z) lies in the bottom of a the recess, whereby the semiconductor device is less susceptible to short-circuit between the p-type base layer (2) and the p layer (3).

Semiconductor thyristor device with recess

In a semiconductor device, a semiconductor element is stored in a casing while being held by external electrodes through first and second electrodes. The outer peripheral edge of the first electrode plate is projected outwardly beyond that of the semiconductor element and a ring-shaped groove is provided in the first surface of the first electrode plate along the outer peripheral edge of the semiconductor element. An adhesive holding member is charged in the groove and the outer peripheral portion of the semiconductor element. Thus, the semiconductor element is fixed to the first electrode plate and is protected by the adhesive holding member covering its end portion.

Semiconductor device and method of assembling the same

A semiconductor structure comprises a gate-turn-off thyristor region (GR) and a diode region (DR) with an isolation area (SR) therebetween. The isolation area is provided with a multistage groove (30) having step structures (34,35). The multistage groove is formed through a two-stage etching process, and over-etched regions in the bottom corners of the multistage groove are relatively shallow ones. This structure is effective for increasing the breakdown voltage of the semiconductor structure and isolations between the gate-turn-off thyristor region and the diode region.

Method of making a groove structure for isolation between elements

A semiconductor structure comprises a gate-turn-off thyristor region (GR) and a diode region (DR) with an isolation area (SR) therebetween. The isolation area is provided with a multistage groove (30) having step structures (34,35). The multistage groove is formed through a two-stage etching process, and over-etched regions in the bottom corners of the multistage groove are relatively shallow ones. This structure is effective for increasing the breakdown voltage of the semiconductor structure and isolations between a the gate-turnoff thyristor region and the diode region.

Groove structure for isolating elements comprising a GTO structure

A flat-pack type GTO thyristor (100) has an external cathode electrode (30) placed on a semiconductor element (1). The top surface of the external cathode electrode has a three-level step configuration (33a, 33b, 33c). When a cathode member (51) of an external electric equipment is pushed onto the external cathode electrode, no force is applied to the lower two steps (33b, 33c) in the step configuration. Consequently, the peripheral portion of the external cathode electrode is not deformed and the semiconductor element does not become unstable in gate characteristics.

Semiconductor device and electrode block for the same

A method of manufacturing a semiconductor device including a semiconductor substrate (10) comprising n-emitter regions (14a-14c) formed before the substrate is brazed on a molybdenum plate (1). Due to the difference between respective thermal expansion coefficients of silicon and molybdenum, the substrate is warped through the brazing process and the horizontal positions of the n-emitter regions are shifted. A mask pattern for patterning an aluminum layer (31) is corrected in position to prevent a patterned aluminum layer from extending over the peripheral areas of the n-emitter regions.

Method of forming pattern in manufacturing semiconductor device

A reverse conducting gate turn-off thyristor has a separating layer (26) in isolating zone (Z) for electrically separating into thyristor and diode portion (X, Z) a p type base layer (22) formed on an n type base layer (21). A gate electrode (29) is formed both on the p type base layer (22) and the separating layer. A portion of the gate electrode (29) on said separating layer serves as a gate collecting electrode (29a). Thus, area for the isolating zone (Z) and the gate collecting electrode (29a) become common, so that the efficiency of utilization of the wafer surface can be increased.

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Fukuoka, Japan

Futoshi Tokunoh