Hitachi, Ltd.

Panasonic Liquid Crystal Display Co., Ltd.

Hitachi Displays, Ltd.

International Superconductivity Technology Center, the Jurdical Foundation

Hitachi Industrial Equipment Systems Co., Ltd.

Futoshi Furuta

Kenichi Osada

Keiji Watanabe

Hiroshi Kageyama

Ken Takei

Kazuo Saitoh

Makoto Saen

Hiromasa Takahashi

Jun Hayakawa

Takao Ishikawa

Kazumasa Takagi

Kazuo Saito

Hiroaki Hasegawa

Takashi Watanabe

Fumiaki Komori

Yoshitaka Morimoto

Akinori Nishide

Shin Yabuuchi

Yuzo Shirakawa

Naoto Fukatani

Takaaki Mizukami

Noboru Kataoka

Shunsuke Matsunaga

Daikoh Takamatsu

Masanori Kurita

A hydrogen production apparatus including a photocatalyst and generating hydrogen from water includes a wavelength separation unit separating sunlight by wavelength, an infrared light conversion unit converting infrared light separated by the wavelength separation unit to visible light, and an ultraviolet light conversion unit converting ultraviolet light separated by the wavelength separation unit to visible light.

Hydrogen production apparatus

To provide a semiconductor device having a high efficiency of arranging a TSV, there is provided a semiconductor device which is stacked with a semiconductor chip, and in which the semiconductor chips contiguous each other are electrically connected by plural TSVs, the semiconductor chip includes a core circuit and plural IO circuits arranged at a surrounding thereof, the TSV is arranged in the core circuit, and a pitch of arranging the TSVs is an integer-fold of a cell pitch of a library configuring the core circuit.

Semiconductor device

In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.

To realize a random number generating circuit that is optimum for a liquid crystal display device that is used in a terminal device that includes a display/input component. A liquid crystal display device includes a liquid crystal display panel, a control circuit and a random number generating circuit, the random number generating circuit comprises plural shift registers, an output circuit and a register that stores an initial value, and the random number generating circuit is equipped with plural initial values, whereby the randomness of the random numbers is improved. Further, it becomes possible to increase and output frequencies by the output circuit because it is possible to output respectively different random numbers from the plural shift registers.

Display device

A communication system by electrostatic coupling and electromagnetic induction includes: a first transmission part () and a first reception part () which exchange data therebetween through non-contact communication using electrostatic coupling; a second transmission part () and a second reception part () which exchange data therebetween through non-contact communication using electromagnetic induction; and an image display device () which displays an image based on the data thus received. With this configuration, it is possible to make communication performed by the first transmission part () and the first reception part () communication with higher speed, larger volume, and higher reliability.

Communication system by electrostatic coupling and electromagnetic induction

A semiconductor integrated circuit device capable of achieving improvement of I/O processing performance, reduction of power consumption, and reduction of cost is provided. Provided is a semiconductor integrated circuit device including, for example, a plurality of semiconductor chips stacked and mounted, the chips having data transceiving terminals bus-connected via through-vias, and data transmission and reception are performed via the bus with using the lowest source voltage among source voltages of internal core circuits of the chips. In accordance with that, a source voltage terminal of an n-th chip to be at the lowest source voltage is connected with source voltage terminals for data transceiving circuits of the other semiconductor chips via through-vias.

Semiconductor integrated circuit device

In order to restrain increase in frame area caused along with a larger number of channels to a minimum, there is provided an image display device that adopts a communication method in which a signal is transmitted/received with the use of electrostatic capacitance coupling. A first board includes: a tabular first power supply line, a tabular second power supply line, a semiconductor element, and a tabular first electrode group. A second board includes: a tabular second electrode group and a tabular common electrode. In a state where the first board and the second board are laid on each other, the first electrode group overlaps the second electrode group while one of the first power supply line and the second power supply line overlaps the common electrode.

Image display device

An image display device includes a display panel having plural pixels and a second board having a transmitting electrode, the display panel having a first substrate that is disposed so as to overlap the second board, each pixel having a pixel electrode and a counter electrode, and the counter electrode being formed in a planar shape and being commonly provided to the pixel electrodes of each pixel; the counter electrode being divided into a portion A corresponding to the transmitting electrode of the second board and a portion B other than it, and the portions A and B of the counter electrode being connected to a common voltage through resistors. The portion A of the counter electrode constitutes the receiving electrode, and the portion A of the counter electrode acting as the receiving electrode is connected to a receiving circuit in the display panel through a decoupling capacitor.

In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.

Semiconductor integrated circuit device comprising a plurality of semiconductor chips mounted to stack for transmitting a signal between the semiconductor chips

Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another. Moreover, by changing the density or phase of a SFQ pulse to be supplied to the Josephson junctions of the integration circuit, the correlativity of quantization noise between the outputs of the modulator circuits is eliminated so that the bit accuracy is improved.

Superconducting single flux quantum modulator circuit

Disclosed is a single flux quantum circuit that uses a flux quantum as an information carrier, which generates a SFQ clock signal with little clock jitter and supplies the SFQ clock signal to a SFQ function circuit of the SFQ circuit, the SFQ function circuit is configured to include a current steering type single flux quantum circuit that is capable of concurrently achieving both a conversion function of converting a current signal into a SFQ signal and a comparator function of outputting a SFQ data signal in response to the amount of a to-be-compared current. At the same time, a SFQ clock signal oscillation circuit for generating a SFQ clock signal in response to the amount of DC voltage is formed.

Current steering type single flux quantum circuit

In an A/D converter having a single flux quantum circuit having a flux quantum as an information carrier, a superconducting amplifier circuit driven by an AC current, and a semiconductor circuit, the operations of the circuits are synchronized with each other and a data signal from the single flux quantum circuit is transmitted to the semiconductor circuit. An AC current as the power source of a superconducting amplifier circuit is inputted as a master clock signal to the single flux quantum circuit and the semiconductor circuit to synchronize the operations of the circuits with the master clock signal. The single flux quantum circuit has a clock signal frequency multiplier circuit, a demultiplexing circuit and a memory circuit.

Superconductor semiconductor integrated circuit

The problem of the disclosed technology is as follows. Although a single flux quantum circuit can fabricate a high-speed sequential circuit with ease, the initialization of the circuit is required for guaranteeing the normal operation of the circuit. However, a prior-art circuit has no initializing function, or requires the restructuring of another logic system. For solving the foregoing problem, one Josephson junction is inserted to a flux quantum storage inductor constituting the existing logic circuit, so that a pulse for performing the circuit initialization is injected to the connection point by means of a comparator.

Growing community of inventors

Kokubunji, Japan

Futoshi Furuta