Fujitsu Corporation

Fujitsu Vlsi Limited

Kyushu Fujitsu Electronics Limited

Fusao Seki

Hiroyuki Kobayashi

Hiroyoshi Tomita

Toshiya Uchida

Shinya Udo

Fumitaka Asami

Tatsushi Otsuka

Shinnosuke Kamata

Masanori Kurita

Masato Abe

Satoru Masaki

Kazuo Ohno

Akinori Yamamoto

Masao Imai

A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

Multiple chip package and IC chips

A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source. The level conversion circuit is supplied with power from the first driving power source, and converts an output signal of the first circuit system into an input signal of the second circuit system. The second circuit system drives a signal with level converted by being supplied with power from the second driving power source. Further, in the semiconductor integrated circuit, a bidirectional level conversion circuit and a signal control means are provided, and the first and the second driving power sources are wired in a lattice form in a semiconductor chip.

Level converter for CMOS 3V to from 5V

A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for shifting the 1/[2n+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the [n-1]th flip-flop circuit of the register synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the nth flip-flop circuit and outputting the 1/[2n+1] frequency-divided signal. A second odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected m [m=3 to m] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2m+1] frequency-divided signal, a register having cascade-connected [m+1] elements of flip-flop circuits for shifting the 1/[ 2m+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the mth flip-flop circuit synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the [m+1]th flip-flop circuit and outputting the 1/[2m+1] frequency-divided signal.

Odd-number frequency divider and method of constituting the same

Growing community of inventors

Kawasaki, Japan

Fusao Seki