Springsoft Usa, Inc.

Novas Software, Inc.

Springsoft, Inc.

Furshing Tsai

Yu-Chin Hsu

Tayung Liu

KunMing Ho

Yirng-An Chen

Kai Yang

Xi Chen

Chieh Changfan

Scott Sandler

Chih Neng Hsu

Jun Zhao

Lu-An Ko

Wori-Tzy Jong

George Bakewell

Ting Shih Ang

Arnold Sher

Wells Woei-Tzy Jong

Bassam Tabbara

Methods for debugging designs are provided. First, signal correlation information for signals of a design at least two design level is obtained. Then, design descriptions corresponding to the design at the at least two design levels are loaded and presented in at least two sets of windows or at least two debugging processes which controls the respective set of windows. A selection of a first signal in a first set of windows or a first debugging process is received. In response to the selection, a second signal corresponding to the first signal is queried according to the signal correlation information, and the second signal in a second set of windows or a second debugging process is automatically selected.

Methods and systems for debugging equivalent designs described at different design levels

A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.

Power-aware debugging

A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump file is converted into an RTL dump file indicating how signals of the RTL design behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results. file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.

Debugging system for gate level IC designs

A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement. Each statement event symbol references the signal whose value is computed by the corresponding statement evaluation and indicates a value of that signal computed when the statement was evaluated. Each statement event symbol also references the other signals having values of which the statement indicates the computed signal value is a function and indicates those other signals values as of the simulation time at which the statement was evaluated.

IC behavior analysis system

A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

System for characterizing simulated circuit logic and behavior

Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data. The system then creates and analyzes a temporally expanded model of the circuit to verify whether, starting from that current state, the circuit will exhibit the consequent behavior within that finite time under all input signal conditions.

Circuit property verification system

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San Jose, CA, United States of America

Furshing Tsai