Other

Stream Machine Company

Fure-Ching Jeng

Cheng-Tie Chen

Ting-Chung Chen

Chia-Chun Huang

Integrated circuit provides single-pass, real-time digital image encoding by digital signal processor for variable bit rate (VBR) control to improve decoded output quality. Possible peak bit rate range for multiple groups of pictures (GOP) and averaged bit rate limit encoded signal bit rate. Possible bit rate range constraint sets upper/lower range, which is pre-specified or dynamically adapted for current and future GOPs. Signal processor calculates perceptual weighting variable at macroblock level for multiple GOPs, nominal quantization parameters for multiple GOPs, quantization parameter associated at picture level, effective bit rate for each GOP, bit allocation for each picture, and total bit allocation for multiple GOPs. Variable rate signal is recordable in DVD or camcorder device.

Single-pass variable bit-rate control for digital video coding

A digital signal processor encodes video signals per MPEG standard to achieve multi-stage, low-complexity motion estimation for interframe video coding. A dual-stage motion prediction module processes a compressed bitstream through pixel-averaging, and then applies a Sum-Of-Absolute-Difference (SOAD) function to the bitstream. A minimum motion vector signal is thereby generated over a search range initially for rough determination, then to provide a more refined estimation, the SOAD function is re-applied to the surrounding 16.times.16 blocks, preferably by full and half-pel vertical and horizontal offsets.

Growing community of inventors

Sunnyvale, CA, United States of America

Fure-Ching Jeng