Taiwan Semiconductor Manufacturing Comp. Ltd.

Fung Song Lee

Li-Chun Tien

Lee-Chung Lu

Yi-Kan Cheng

Yuan-Te Hou

Wen-Ju Preet Yang

Huang-Yu Chen

Gwan Sin Chang

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of Gpaths exists in the row of cells, or no double-patterning full trace having an odd number of Gpaths exists in the row of cells.

Methods for double-patterning-compliant standard cell design

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

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Banciao, Taiwan

Fung Song Lee