Avago Technologies Ecbu IP (singapore) Pte. Ltd.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Fun Kok Chow

Gek Yong Ng

Kah Weng Lee

Qian Tao

Lei Chen

Bin Zhang

Kwee Chong Chang

Chee Heng Wong

Kok Keong Richard Lum

Richard Kok Keong Lum

Peng Siang Seet

Jia Peng

In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device comprising a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further comprises an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.

Isolation device

An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may have a transmitter coupled to a modulator that modulates the first signal. The second semiconductor die may have a receiver having a counter and a control circuit. The control circuit may be adapted to determine an indication of the first signal by using the counter. In addition, an isolation system and a DC-DC feedback regulation control system having such control circuit are disclosed. Likewise, a method for conveying a first signal across an isolation barrier is disclosed. The method may comprise counting a received signal based on internal clock and determining an indication of the first signal from the counter's count value.

Isolation device and system

In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device having a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further has an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.

According to one embodiment, there is provided a method of reducing the amount of power consumed by a galvanic isolator. A transmitter transmits a wake-up signal to a receiver located across an isolation medium when the transmitter is ready or preparing to transmit data or power signals to a receiver, which is operably connected to a sensing circuit. The sensing circuit receives the wake-up signal through the isolation medium, which may be operably connected to and powered substantially continuously or intermittently by a first power source. In response to the sensing circuit receiving the wake-up signal, the receiver is powered up from a sleep mode to an operating mode. After a period of time thas passed since the wake-up signal was transmitted, a signature pattern is transmitted from the transmitter to the sensing circuit through the isolation medium. Next, the sensing circuit or the receiver verifies the validity of the signature pattern. If the signature pattern is determined at to be valid, the receiver is enabled to receive the data or power signals from the transmitter. The transmitter then transmits the data or power signals from the transmitter through the isolation medium to the receiver.

Wake-up circuits, devices and methods for galvanic isolators

According to one embodiment, there is provided a high voltage isolation dual capacitor communication system comprising communication drive and sense electrodes and corresponding first and second capacitors that are formed in two separate devices. The two devices are electrically connected in series to provide a single galvanically-isolated communication system that exhibits high breakdown voltage performance in combination with good signal coupling. The system effects communications between drive and receive circuits through the first and second capacitors, and in a preferred embodiment is capable of effecting relatively high-speed digital communications. The system may be formed in a small package using, by way of example, CMOS or other semiconductor fabrication and packaging processes.

High voltage isolation dual capacitor communication system

According to one embodiment, there is provided an optocoupler system configured to generate current signals having high, low and no amplitude portions in response to the receipt of logic high and low input signals. The varying amplitude portions of the current signals are used to drive other portions of the isolation circuitry, and result in reduced power consumption and dissipation, as well as reduced pulse width distortion.

Optocoupler system with reduced power consumption and pulse width distortion

An integrated circuit battery sensor and system thereof are provided. The battery sensor includes a voltage sensor configured to sample a voyage of a battery and a buffer in electrical communication with the voltage sensor and configured for scaling the sampled battery voltage and outputting a voltage signal proportional to the sampled battery voltage; wherein the voltage sensor is further configured for isolating the buffer from the battery. The voltage sensor includes a first capacitor coupled to a positive potential terminal of the battery and a second capacitor coupled to a negative potential terminal of the battery. The battery sensor includes a first die including a first and second input terminal configured for coupling to the positive and negative potential terminals of the battery; and a second die including the voltage sensor, wherein the first and second die are electrically isolated from each other.

Integrated battery voltage sensor with high voltage isolation, a battery voltage sensing system and methods therefor

According to one embodiment, there is provided a high voltage drive circuit comprising drive and sense electrodes formed substantially in a single plane. The device effects signal transfer between drive and receive circuits through the drive and sense electrodes by capacitive means, and permits high voltage devices, such as IGBTs, to be driven thereby without the use of high voltage transistors, thereby eliminating the need to use expensive fabrication processes such as SOI when manufacturing high voltage gate drive circuits and ICs. The device may be formed in a small package using, by way of example, using CMOS or other conventional low-cost semiconductor fabrication and packaging processes.

High voltage drive circuit employing capacitive signal coupling and associated devices and methods

According to one embodiment, there is provided a semiconductor digital communication device comprising communication drive and sense electrodes formed in a single plane, where the electrodes have relatively high sidewalls. The relatively high sidewalls permit low electrical field densities to be obtained in the sense and drive electrodes during operation, and further permit very high breakdown voltages to be obtained between the electrodes, and between the drive electrode and an underlying ground plane substrate. The device effects communications between drive and receive circuits through the drive and sense electrodes by capacitive means, and in a preferred embodiment is capable of effecting relatively high-speed digital communications. The device may be formed in a small package using, by way of example, CMOS or other semiconductor fabrication and packaging processes.

High voltage isolation semiconductor capacitor digital communication device and corresponding package

An optically isolated circuit device includes a first opto-isolator circuit that is driven by a first clock signal, and the output of the first opto-isolator circuit is used to drive a phase-locked loop (PLL) that is configured to synthesize a second clock signal having a frequency that is a multiple of the first clock signal frequency. The second clock signal is used as an input to a suitable clocked circuit of a type that benefits from optical isolation, such as an analog-to-digital converter (ADC).

High immunity clock regeneration over optically isolated channel

In one embodiment, apparatus is provided with current optimization logic, a programmable current source for generating a reference current threshold, and current programming logic. In response to a plurality of input pulses received by a first TIA, the current optimization logic produces a series of digitized current values in response to i) a signal correlated to an output of the first TIA, to ii) a reference signal to which the output of the first TIA is compared. The current programming logic i) programs the programmable current source using ones of the series of digitized current values, until a predetermined condition is met, and then ii) locks the programmable current source to a most recent one of the digitized current values. In response to the reference current threshold, a second TIA produces the reference signal.

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Singapore, Singapore

Fun Kok Chow