Kabushiki Kaisha Toshiba

Fumiyuki Yamane

Takashi Akiba

Shuji Ono

Tadahiro Kuroda

Kazuto Kuroda

Masataka Matsui

Toshinari Takayanagi

Mami Mizutani

Shinichiro Kosugi

Nobuo Shibuya

Ryuichi Morikawa

Tetsu Nagamatsu

Yuki Kuwano

Yasuo Unekawa

Yasuhiro Miyamoto

Yuuki Kuwano

A battery pack for an electrically driven automobile includes plural battery banks, a battery management unit that detects current flows, voltages and temperatures, first and second terminals connected respectively to the positive and negative electrode terminals of the battery banks, plural third and fourth terminals connected respectively to the positive and negative electrode terminals of the battery banks, a main contactor that switches the connection between the positive electrode terminals of the battery banks and the first terminal and the connection between the negative electrode terminals of battery banks and the second terminal, sub-contactors that switch the connection between the positive electrode terminals of the battery banks and the first terminal, and charging sub-contactors that switch the connection between the positive electrode terminals of the battery banks and the third terminals and the connection between the negative electrode terminals of the battery banks and the fourth terminals, respectively.

Battery pack and electrically driven automobile

According to one embodiment, the power supply management portion includes a timer configured to output an ON signal every time set by the control circuit, an OR circuit configured to receive supply of an output signal from the timer, an external signal supplied from outside, and a switch control signal output from the control circuit, and a switch circuit configured to switch output of the power source voltage from an external power source according to an output signal from the OR circuit, and the control circuit turns on a switch control signal after confirming which of the output signal from the timer or the external signal has turned on the switch circuit and turns off the switch control signal when both of the output signal from the timer and the signal supplied from outside are turned off.

Secondary battery device and vehicle

A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout region into plurality; calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells; adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition is not violated; and optimizing hold timing of the cells after the position adjustment of the cells.

Method for designing semiconductor integrated circuit

A DLL circuit includes an input circuit generating a synchronization reference signal, a first delay unit delaying the synchronization reference signal to generate a plurality of delayed synchronization reference signals and selecting one of the delayed synchronization reference signals, a timing offset circuit adjusting a synchronization position of the delayed synchronization reference signal to generate a signal to be synchronized, a phase comparison circuit comparing phase of the synchronization reference signal with that of the signal to be synchronized, a first control circuit selecting an output signal of the first delay unit, a second delay unit delaying the synchronization reference signal or the signal to be synchronized to generate a plurality of delayed signals, a configuration information memory storing configuration information, and a second control circuit selecting an output signal of the second delay unit if the comparison result of the phase comparison circuit is within a predetermined range.

DLL circuit

A semiconductor integrated circuit has a plurality of clock tree cells arranged in a tree structure on clock signal lines transmitting a clock signal, the plurality of clock tree cells forming a clock tree. The clock tree cells include first power supply lines connected to the clock tree cells, second power supply lines connected to logic circuits receiving a clock signal supplied from the clock tree, and a plurality of power supply pads connected to the first power supply lines and the second power supply lines.

Semiconductor integrated circuit

A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each of the first delay units being configured to output a delayed signal of the reference signal, a blocking circuit inserted between the first delay units, the blocking circuit being capable of switching between passing and blocking an input delayed signal of the reference signal, and the delay time of the blocking circuit being integer times as large as each of the delay time of the first delay units, and one or more second delay units connected in parallel with the blocking circuit, the same signal as the delayed signal that is input in the blocking circuit being input in the second delay units, each of the second delay units being configured to output a delayed signal of the reference signal, and the delay time of each of the second delay units being equal to the delay time of each of the first delay units; and a blocking control circuit configured to control the blocking circuit whether to pass or block the delayed signal that is input in the blocking circuit.

A DLL circuit has an input circuit configured to generate a synchronization reference signal on the basis of an input signal, a first delay unit configured to delay the synchronization reference signal, a timing offset circuit configured to adjust a synchronization position of the synchronization reference signal delayed by the first delay unit to generate a signal to be synchronized, a phase comparison circuit configured to compare phase of the synchronization reference signal with that of the signal to be synchronized, a first control circuit configured to select an output signal of the first delay unit on the basis of a comparison result of the phase comparison circuit, a second delay unit configured to delay the synchronization reference signal or the signal to be synchronized and a second control circuit configured to select an output signal of the second delay unit in the case where the comparison result of the phase comparison circuit is within a predetermined range. The phase comparison circuit compares the phase of the signal, which is either the synchronization reference signal or the signal to be synchronized, delayed by the second delay unit with the phase of the other signal.

A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data. Since data written in the memory cell suffices to have a potential difference smaller than the potential difference between the power supply potential and the ground potential, the time required to drive the bit line having a large load capacitance is shortened, the power consumption is decreased, and the power consumption necessary for writing data in the memory cell is reduced.

Growing community of inventors

Kawasaki, Japan

Fumiyuki Yamane