Fujitsu Corporation

Fumiyasu Hirose

Hidetoshi Matsuoka

Koichiro Takayama

Shintaro Shimogori

Minoru Shoji

Hiroaki Iwashita

Tsuneo Nakata

Satoshi Kowatari

Kioto Hirahara

All nodes in a network are classified into hierarchical groups. Each node belongs to any group in all hierarchical groups from the highest order group to the lowest order group. The node is assigned a hierarchical address corresponding to each hierarchical group. Thus, the amount of routing information required for data transfer can be reduced, thereby efficiently transmitting data.

Node grouping method and data transmitting method in a network

Data transferring buffer circuits for data exchange include a plurality of buffers corresponding to a plurality of data sources for independently receiving and storing data sent from the plurality of data sources, and a buffer limit signal generating circuit for delivering a buffer limit signal when the amount of data stored in a buffer reaches a predetermined limit. The buffer circuits also include a data read signal generating circuit for selecting one of the buffers and generating a data reading signal for the selected buffer. The data reading signal is generated based on a remaining amount of data and information concerning a vacancy at a buffer to which data is to be supplied. The buffer circuits also include a selected data delivery circuit for adopting data selected by the data read signal generating circuit and for delivering the adopted data.

Data transferring buffer

First, an initial operation model M.sub.0 of a pipeline is configured according to the pipeline configuration of a processor and the specification information about an instruction executed by the processor. Then, the number of the states of the initial operation model M.sub.0 is minimized to configure an operation model M. Based on the operation model M and a test state set H, listed are test instruction strings for the process in which the state of the operation model M indicates a transition from a predetermined input state to any of the test states contained in the test state set H without an occurrence of a conflict in the operation model M. A next time state, reached after the state of the operation model M has reached the test state of the test instruction string, is calculated and the next time state is input as a new input state to a test instruction string listing unit.

Automatic instruction string generation method and device for verifying

A uniform load distributing method for use in executing a parallel processing in a parallel computer for executing a plurality of processings in parallel manner. The parallel computer including a plurality of processors for executing individual processings, a network for conducting communication between the plurality of processors, and a synchronizing mechanism for issuing an execution start command for a next step to all the processors under the condition that a completion information of the processing is received from all the processors and the inter-processor communication in the network has been completed. All the processors are synchronized with one another in each step and process calculation of a multitude of individual processings in parallel manner by executing by the respective processors only the individual the individual processings processings whose output data in a current step are used immediately in a next step when all the data necessary for the multitude of individual processings are ready in the step wherein the respective processors execute the processings; informing of the synchronizing mechanism the completion of the execution, immediately after the execution has been completed, to the synchronizing mechanism; and executing, during a waiting time until the execution start command for the next step is given from the synchronizing mechanism, by the respective processors, the individual processings whose input data required for the execution are ready and whose output data are used at an earliest timing after the next step.

Uniform load distributing method for use in executing parallel

A logic simulation method and apparatus for sequentially performing a high-speed simulation of a logic circuit designed through sequential processing descriptions. An operation control unit corresponds to each of a plurality of operations described in sequential processing descriptions. The operation control unit controls a start of an operation and determines an end of the operation. After determining an end of a first operation by simulating operation of the operation control unit corresponding to the first operation, a next operation described in sequential processing descriptions is simulated concurrently with simulating an operation control unit corresponding to the next operation until all operations have been sequenced through.

Logic simulation method

A variable logic operation apparatus which receives n-nary input data, logic function setting data and connection data, and performs logic operations on the input data based on a logic expression. The apparatus includes a plurality of logic operation units, each logic operation unit selecting a respective logic operation from a group of at least one logic operation, and outputting a single result based on the selected logic operation. The selected logic operation is selected by the logic function setting data. A plurality of connection devices connect the plurality of logic operation units in accordance with the connection data to form a tree structure. The tree structure is changeable by changing the connection data. Thus, the logic expression is converted into the tree structure in accordance with the setting data and the connection data.

Variable logic operation apparatus

A gate addressing system of a logic simulation machine performs translation from data of a circuit design data base to circuit data for the logic simulation machine. The system numbers each input terminal of a circuit and each gate of said circuit without using numbers corresponding to the number of fanout gates minus one to which an output signal of an input terminal or a gate is applied between the numbers of one input terminal and another input terminal, one input terminal and one gate, one gate and another gate or one gate and one input terminal. It starts a list of numbers of fanout gates of each input terminal or each gate at an address as the number assigned to said input terminal and gate in a table representing connection relationships among input terminals and gates and among gates.

Gate addressing system for logic simulation machine

A gate processor arrangement for a logic simulation processor system includes a new event buffer memory for storing an event at a timing t.sub.a for a predetermined logic element in a section of a logic network. A fan-out device for holding connection information for the predetermined logic element in the section of the logic network and reading the data of the predetermined logic element precedingly at a timing t is also provided. The input data of the predetermined logic element is changed at a timing 't+1'. An evaluation gate buffer memory is provided having a plurality of evaluation gate memory portions able to be connected to the fan-out device and an evaluation device. The arrangement also includes a net status memory for holding net status information corresponding to input data and output data of a predetermined logic element in the section of the logic network; and an evaluation device responsive to the output of the evaluation gate buffer memory for reading the data in the net status memory, generating information for the change of the network status at a timing 't+1', and supplying the generated information to the event transmission network and/or the new event buffer memory.

Growing community of inventors

Kawasaki, Japan

Fumiyasu Hirose