Kioxia Corporation

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Fumiya Watanabe

Masaru Koyanagi

Mikihiko Ito

Shouichi Ozaki

Kensuke Yamamoto

Yasuhiro Hirashima

Kei Shiraishi

Toshifumi Watanabe

Kenro Kubota

Kazuhiko Satou

Harumi Abe

Ryota Tsuchiya

Atsuko Saeki

Satoshi Inoue

Kosuke Yanagidaira

Yutaka Shimizu

Yumi Takada

Taichi Wakui

A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.

Semiconductor memory device having a control circuit for changing a drive capability of an output circuit of the semiconductor memory device

A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

Semiconductor device

In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

Semiconductor integrated circuit and semiconductor storage device

A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.

A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Semiconductor storage device and memory system in which control circuit of the semiconductor storage device executes calibration operation according to timing at which data is read from another semiconductor storage device

According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.

Nonvolatile memory and memory system

A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.

Semiconductor memory device

According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second P-type transistors; a second amplifier circuit including first and second N-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second P-type transistors. The third and fourth current mirror circuits are connected to drains of the first and second N-type transistors. The sixth current mirror circuit is connected to the first, fourth and fifth current mirror circuits. The seventh current mirror circuit is connected to the second, third and fifth current mirror circuits.

Semiconductor amplifier circuit

According to one embodiment, a semiconductor device includes: a first circuit including a first transistor, a second transistor, the first and second transistors being capable of receiving first and second signals, respectively; a second circuit including a third transistor and a fourth transistor, a gate and one end of the third transistor being connected to one end of the first transistor, the fourth transistor being capable of receiving the first signal, one end of the fourth transistor being connected to the other end of the third transistor; and a third circuit configured to charge or discharge a node being connected to the one end of the first transistor according to the first signal.

Growing community of inventors

Yokohama Kanagawa, Japan

Fumiya Watanabe