Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fumitoshi Sugimoto

Yoshihiro Arimoto

Isamu Hanyu

Tatsuya Ohori

Sadahiro Kishii

Kazunori Imaoka

Takao Miura

Kiyoshi Ozawa

Hiroshi Horie

A mask formed with a mask pattern is prepared, the mask pattern having a shape that a base pattern is divided into at least two partial patterns disposed at a space narrower than a resolution limit. A first relation is acquired between a width of the space separating the partial patterns and a size of a pattern on a substrate formed by transferring the mask pattern. The width of the space separating the partial patterns is determined in accordance with the size of a pattern to be formed on the substrate and the first relation. A mask pattern is formed having at least two separated partial patterns on a mask in accordance with the determined width of the space.

Exposure mask, its manufacture method, pattern transfer method, pattern forming method, and SRAM manufacture method

In order to form a transfer pattern of desired size with high accuracy, a method for manufacturing a semiconductor device includes a process of forming the transfer pattern including a line whose width and angle varies, by performing multiple exposure using a plurality of masks having different patterns over different mask substrates.

Semiconductor device manufacturing method, mask manufacturing method, and exposure method

The method for fabricating the semiconductor device includes the step of forming a photoresist filmover a substrate, the step of exposing interconnection patterns to the photoresist film, the step of exposing to the photoresist filmhole patterns of a plurality of holes positioned at ends or bent portions of the interconnection patterns where holes to be connected to the interconnection patterns are to be formed, and the step of developing the photoresist filmwith the interconnection patterns and the holes patterns exposed to. Thus, the insufficient exposure energy at the ends or the bent portions of the patterns due to optical proximity effect is compensated to prevent the shortening at the pattern ends or the rounding at the pattern bent portions. The contacts with the contact plugs connected to the pattern ends or the pattern bent portions can be ensured.

Method for fabricating semiconductor device and exposure mask

An exposure method executed after processing a hole in a substrate of a semiconductor device, has an exposure step of transferring a pattern on a mask onto an upper layer of the hole and forming a wiring groove by exposure, wherein a quantity of exposure with which a wiring groovejust above the hole or the wiring groove in the vicinity of the hole is exposed to light, is greater than a quantity of exposure with which a wiring grooveA in a position spaced away from just above the hole is exposed to the light.

Exposure method for upper layer of hole of semiconductor device

An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.

Apparatus and method for uniformly polishing a wafer

A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.

Composite semiconductor substrate having a single crystal substrate and

A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.

Composite semiconductor substrate and a fabrication process thereof

In a direct bonded SOI substrate where the SiO.sub.2 films OA, OB are respectively provided on the single surfaces of the silicon substrates A, B, at least any one of SiO.sub.2 films OA, OB has thickness of 1 .mu.m or more. These SiO.sub.2 films OA, OB are bonded and moreover the one silicon substrate B of such a bonded substrate is ground to thickness of about 1 .mu.m. A semiconductor device having a trench structure wherein the trench formed on the silicon substrate B passes through the interface between the SiO.sub.2 film OB and the SiO.sub.2 film OA. The bottom of such a trench is located within the SiO.sub.2 film OA and the bottom of the polycrystalline silicon conductive film within the trench is located within the SiO.sub.2 film OA rather than the interface between the silicon substrate B and SiO.sub.2 film OB.

Growing community of inventors

Kawasaki, Japan

Fumitoshi Sugimoto