Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Fumitoshi Hatori

Kazutaka Nogami

Hiroyuki Hara

Shinichiro Shiratake

Tetsuya Fujita

Yukihito Oowaki

Takayasu Sakurai

Mototsugu Hamada

Masataka Matsui

Makoto Takahashi

Kojiro Suzuki

Makoto Ichida

Masanori Uchida

Fuyuki Ichiba

A wireless communication apparatus includes a transmission/reception unit, a measurement unit, a physical layer, an acquisition unit, and a control unit. The transmission/reception unit transmits/receives packets to/from a communication peer. The measurement unit starts measuring a time period after a predetermined time from an end of the packet transmitted to the communication peer. The physical layer detects a synchronization code included in the packet transmitted from the communication peer and generates a synchronization detection signal. The acquisition unit acquires a measured value by the measurement unit when receiving the synchronization detection signal. The control unit has a function to change the physical layer to a physical layer with a different error tolerance, and calculates a propagation delay by subtracting a length of a synchronization code from the measured value and judges whether to update the physical layer or not depending on the propagation delay.

Wireless communication apparatus and wireless communication system

A semiconductor integrated circuit, operable in a normal mode and a test mode, includes a demodulator, a demodulated signal processing section, a header analysis section, a payload processing section, and a control section. The demodulator demodulates a modulated wireless signal including a synchronization pattern, header, and payload, to generate a demodulated signal. The demodulated signal processing section detects the synchronization pattern from the demodulated signal, generates a synchronization detection signal synchronized to the synchronization pattern, and converts the demodulated signal into a received bit sequence. The header analysis section extracts and analyzes the header to obtain the number of bits of the payload. The payload processing section processes the payload. The control section disables the demodulator when processing of the number of bits in the payload is completed in the normal mode, and disables the demodulator synchronously with a signal indicating the end of a test in the test mode.

Semiconductor integrated circuit and test method thereof

According to one embodiment, a semiconductor integrated circuit includes a first circuit, a second circuit, and a signal propagation control circuit. The first circuit is configured to have a first power supply terminal. The second circuit is configured to have a second power supply terminal independent of the first power supply terminal. The signal propagation control circuit is configured to provide a first fixed value to the second circuit for a predetermined period after power is supplied to the second circuit, and after the predetermined period, configured to control whether to transfer an output signal from the first circuit to the second circuit or provide the first fixed value to the second circuit.

Semiconductor integrated circuit and system of controlling the same

According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

Semiconductor device and system

A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

Semiconductor integrated circuit having controller controlling the change rate of power voltage

A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

Semiconductor device adapted to minimize clock skew

An object of the present invention to provide a pulse width modulation waveform generating circuit that it is possible to reduce circuit size and power consumption. A pulse width modulation waveform generating circuit comprises a ring oscillator having 64 pieces of inverters connected in series, inverters connected to output terminals of odd numbered stages of inverters in the ring oscillator, a multiplexer, a change detecting circuit, and an RS flip-flop. The multiplexer is supplied with output signals of even numbered stages of the inverters in the ring oscillator and output signal of the inverter. One of their signals is selected in accordance with logic of a digital signal. The RS flip-flop is set at time an edge detecting pulse is outputted from the change detecting circuit, and is reset at time an edge detecting pulse is outputted from the change detecting circuit.

Pulse width modulation waveform generating circuit

Semiconductor device

A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.

Memory circuit

A programmable semiconductor integrated circuit constructed as a Field Programmable Gate Array (FPGA) comprises basic cells each comprised of; a first stable circuit having first and second nodes and operative to respectively output, in the steady state, power supply potential and ground potential from the first and second nodes; a second stable circuit having third and fourth nodes and operative to respectively output, in the steady state, ground potential and power supply potential from the third and fourth nodes; and a control circuit for selectively connecting any one of a node pair comprised of the first and second nodes of the first stable circuit and a node pair comprised of the third and fourth nodes of the second stable circuit, or the both node pairs to first and second bit lines.

Programmable semiconductor integrated circuit

A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively. Wiring of different lengths is provided for connecting circuit elements within the field programmable gate array, with wires of a first length being more numerous than wires of a second, longer length. The quantity of wires of different lengths varies in accordance with the -2.5 power of the length of the wires.

Field programmable gate array having transmission gates and

A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . . ) between which the programmable element to be programmed is connected and an intermediate voltage between the first and second wirings between which the programmable element not to be programmed is connected, the intermediate voltage being lower than the programming voltage to such an extent as not to affect state of the programmable elements (A11, A12, A13, . . . ).

Field programmable gate array

A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.

Growing community of inventors

Yokohama, Japan

Fumitoshi Hatori