Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Semiconductor Manufacturing International Corp.

Fumitake Mieno

Min-Hwa Chi

Youfeng He

Hua Ji

David Gao

Roger Lee

Guoqing Chen

Sean Fuxiong Zhang

Meisheng Zhou

A method for manufacturing a semiconductor device may include forming a semiconductor portion, forming a doped portion, and forming a dielectric member. A side of the dielectric member abuts each of the semiconductor portion and the doped portion. A first half of the doped portion is positioned between the semiconductor portion and a second half of the doped portion. A dopant concentration of the second half of the doped portion is greater than a dopant concentration of the first half of the doped portion.

Semiconductor channel-stop layer and method of manufacturing the same

A gate electrode and method for manufacturing the same includes an amorphous gate metal layer. The amorphous gate metal layer includes an amorphous metal alloy material layer having at least two metallic elements of an amorphous material or an amorphous metal compound material layer having at least one metallic element and at least one non-metallic element selected from the IIIA group, the IVA group, and the VA group of the Periodic Table. The atoms are arranged evenly in the amorphous gate metal layer, there is no noticeable grains and grain boundaries, so that no defects will be generated through a carrier recombination, and the carrier mobility is increased and the carrier can be uniformly distributed.

Metal gate stack structure and manufacturing method

A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.

Method for manufacturing semiconductor device with tensile stress

A semiconductor device includes a semiconductor fin on a substrate. The semiconductor fin includes a stack of alternating layers of first and second materials that induce stress or strain to the channel of the semiconductor device for implementing a strained FinFET. The first and second materials are different. The second material layers include lateral recesses filled with an insulating layer to form an isolated FinFET structure to further induce stress in the channel region to improve the performance of the semiconductor device.

Segregated FinFET structure and manufacturing method

A resistive memory storage device includes a lower electrode, an upper electrode and a plurality of composite material layers disposed between the lower electrode and the upper electrode. Each composite material layer includes a first layer and a second layer. The first layer is a metal-based high-K dielectric material layer having a first metal element, and the second layer is a metal layer having the first metal element.

Resistive random access memory device and manufacturing methods

The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device comprises: a gate structure located on a substrate, Ge-containing semiconductor layers located on the opposite sides of the gate structure, a doped semiconductor layer epitaxially grown between the Ge-containing semiconductor layers, the bottom surfaces of the Ge-containing semiconductor layers located on the same horizontal plane as that of the epitaxial semiconductor layer. The epitaxial semiconductor layer is used as a channel region, and the Ge-containing semiconductor layers are used as source/drain extension regions.

Semiconductor device and manufacturing method thereof

A FinFET device includes a gate dielectric layer on a substrate, a fin on the gate dielectric layer having a middle section and source and drain regions at opposite ends, and a gate structure on the middle section of the fin. The FinFET device also includes a trench in a portion of the source and drain regions and a multi-layered epitaxial structure in the trench. The multi-layered epitaxial structure includes a first epitaxial layer in direct contact with the bottom of the trench, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is a carbon-doped silicon layer having a carbon dopant concentration of less than 4 percent by weight, the second epitaxial layer is a barrier metal layer, and the third epitaxial layer is a metal layer.

Fin-type field effect transistor and manufacturing method thereof

This disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a patterned stacked structure formed on a semiconductor substrate, the stacked structure comprising a silicon-containing semiconductor layer overlaying the semiconductor substrate, a gate dielectric layer overlaying the silicon-containing semiconductor layer and a gate layer overlaying the gate dielectric layer; and a doped epitaxial semiconductor layer on opposing sides of the silicon-containing semiconductor layer forming raised source/drain extension regions. Optionally, the silicon-containing semiconductor layer may be used as a channel region. According to this disclosure, the source/drain extension regions can be advantageously made to have a shallow junction depth (or a small thickness) and a high doping concentration.

A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an Npolysilicon layer on a diffusion barrier layer which is on a first conductive layer. The Npolysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a Ppolysilicon layer overlying the co-planar surface and a floating gate on the Ppolysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a Ppolysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

TFT floating gate memory cell structures

The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.

Phase change memory

A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiHthermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiHthermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.

Method of epitaxially growing silicon by atomic layer deposition for TFT flash memory cell

A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.

Semiconductor device and related manufacturing method

A fin field effect transistor and a method for forming the fin field effect transistor are provided. In an exemplary method, the Fin FET can be formed by forming a dielectric layer and a fin on a semiconductor substrate. The fin can be formed throughout an entire thickness of the dielectric layer and a top surface of the fin is higher than a top surface of the dielectric layer. The fin can be annealed using a hydrogen-containing gas and a repairing gas containing at least an element corresponding to a material of the fin. A gate structure can be formed on the top surface of the dielectric layer and at least on sidewalls of a length portion of the fin after the annealing process.

Fin field effect transistor and fabrication method

A semiconductor device includes a substrate having an active region, a gate structure on the active region, and spacers formed on opposite sides of the gate structure. The gate structure includes a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and sidewalls on both side surfaces of the gate structure. Each of the sidewalls is interposed between the metal gate and one of the spacers. The sidewalls include a self-assembly material. The gate dielectric layer includes a high-K material. The spacers include silicon nitride. The gate structure also includes a buffer layer interposed between the metal gate and the gate dielectric layer.

The present invention provides a transistor and a method for forming the same. The method includes: providing a semiconductor substrate having a semiconductor layer formed thereon, the semiconductor layer and the semiconductor substrate having different crystal orientations; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the semiconductor substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer, which is substantially flush with the dummy gate structure; removing the dummy gate structure and the semiconductor layer beneath the dummy gate structure, forming an opening in the interlayer dielectric layer and the semiconductor layer, the semiconductor substrate being exposed at a bottom of the opening; forming a metal gate structure in the opening. Saturation current of the transistor is raised, and performance of a semiconductor device is promoted.

Growing community of inventors

Shanghai, China

Fumitake Mieno