Fujitsu Corporation

Kyushu Fujitsu Electronics Limited

Other

Hitachi, Ltd.

Fujitsu Hitachi Plasma Display Limited

Fujitsu Vlsi Limited

Hitachi Plasma Patent Licensing Co., Ltd.

Fumitaka Asami

Tomokatsu Kishi

Yoshikazu Kanazawa

Shigetoshi Tomio

Tadatsugu Hirose

Toshio Ueda

Shinya Udo

Tomoyuki Ishii

Takashi Sasaki

Hitoshi Hirakawa

Noboru Akiyama

Michitaka Ohsawa

Makoto Onozawa

Yuji Sano

Naoki Matsui

Toyoshi Kawada

Masato Abe

Kazuo Yoshiikawa

Kenji Awamoto

Masaya Tajima

Takashi Fujisaki

Yoshimasa Awata

Tetsuo Aoki

Kiyoshi Takata

Junichi Okayasu

Osamu Takagi

Hisashi Yamaguchi

Shinsuke Tanaka

Katsuhiro Ishida

Kazuhiro Takahara

Seiji Yamagata

Masami Oda

Nobuyoshi Kondo

Tadahisa Yamaguchi

Noriko Kadomaru

Norio Matsumoto

Hideki Isohata

Fusao Seki

Masatoshi Hira

Satoru Masaki

Kazuo Ohno

Shinichi Sekine

Akinori Yamamoto

Motoki Shimozono

Kazuyuki Harada

Masao Imai

Syouichi Tanigashira

Yukinori Kamizono

Tadao Miyasaka

A method for driving a plasma display panel, including a plurality of display electrode pairs and a plurality of address electrodes, and which includes at least an address period and a sustain discharge period. In the address period, performing address processing, between the address electrodes and a display electrode configured as either a set of odd or even numbered display electrodes, sequentially to all of one of the sets of display electrode pairs, and thereafter address processing, between the address electrodes and a display electrode configured as the other set of display electrode pairs, sequentially to all of the other set of display electrode pairs. In the sustain discharge period, supplying at least one first sustain discharge pulse to the one set of display electrode pairs, and supplying at least one second sustain discharge pulse to the other set of display electrode pairs.

Method for driving a plasma display panel

A display apparatus includes a display panel including address electrodes and sustain electrodes crossing the address electrodes, with pixels being sandwiched between the address electrodes and the sustain electrodes. A sustain-electrode drive circuit selectively generates both sustain pulses and scan pulses and supplies them to the sustain electrodes. An address-electrode drive circuit generates address pulses based on a video signal and supplies the address pulses to the address electrodes. A control-signal generation circuit generates a control signal for controlling the sustain-electrode drive circuit to generate a selected one of the sustain pulses and the scan pulses and supplies the control signal to the sustain-electrode drive circuit. In order to display an image on the display panel, the sustain-electrode drive circuit both specifies addresses of pixels to be turned on and turns on the pixels at the specified addresses.

Display apparatus

Method for driving a plasma display panel. At least one first discharge sustaining pulse is applied to a first pair of display electrodes, and at least one second discharge sustaining pulse applied to an adjacent pair of display electrodes. The first and second discharge sustaining pulses are applied such that they are in the same phase as one another and/or such that a current in the first pair of display electrodes flows in the opposite direction from a current in the adjacent pair of display electrodes.

Method of driving plasma display panel by applying discharge sustaining pulses

A display has a panel, and first and second electrodes. The first and second electrodes define a matrix of cells on the panel. The second electrodes, which correspond to lines of the cells, are scanned to select the cell lines one by one. The first electrodes are driven to set display data for a selected one of the cell lines. The display also has a sequence setting unit for setting sequences of scanning the second electrodes, and a sequence selection unit for selecting one of the sequences that minimizes the current and power consumption of a first-electrode driver without deteriorating the quality of the displayed images.

Display and method of driving the display capable of reducing current and power consumption without deteriorating quality of displayed images

A plasma display device has a pair of substrates having electrodes and terminals provided at ends of the electrodes. Driving circuits supply a driving voltage to the electrodes via flexible printed circuit boards to emit light. Connectors are detachably attached to the substrate. The connector includes a housing and terminal members disposed in the housing, with the terminal member having a U-shaped cross-sectional shape, so that a first portion as one leg of the &ldquo;U&rdquo; contacts the terminal of the electrode and a second portion as another leg of the &ldquo;U&rdquo; contacts the conductor of the flexible connecting member. The terminals of the electrodes are arranged in a staggered manner at the end of the substrate.

Plasma display device with flexible circuit boards and connectors

An electrode drive circuit performs interlaced scanning, ensuring that the phases of the sustaining pulse in odd-numbered lines and even-numbered lines among L to L between surface discharge electrodes are the reverse of each other. With this, when either odd-numbered lines or even-numbered lines are displayed, the voltages applied between the electrodes of the undisplayed lines are at 0, eliminating the necessity for partitioning walls on the surface discharge electrodes. In surface discharge electrodes, X electrodes are provided on the two sides of a Y electrode and the area between the Y electrode and the X electrode on one side is assigned a display line at an odd-numbered frame, and the area between the Y electrode and the X electrode on the other side is assigned a display line in an even-numbered frame. Alternate areas between the surface discharge electrodes are assigned as blind lines and a discharge light emission in the blind lines is blocked or incident light to the blind lines from the outside is absorbed. Address electrodes are provided for each monochromatic pixel column and selectively connected with the pads above them, performing simultaneous selection of lines.

Plasma display panel, method of driving same and plasma display apparatus

As is obvious from the description in the specification and the attached drawings, the present invention provides a display apparatus for displaying an image on a display panel by turning on pixels of said display panel, said display apparatus comprising: a display panel provided with: address electrodes driven by address pulses based on a video input signal; and sustain electrodes crossing said address electrodes and sandwiching electrical discharging units of pixels with said address electrodes and driven by sustain pulses; a sustain-electrode drive circuit for generating said sustain pulses and scan pulses, provided with a common circuit for generating said sustain pulses or said scan pulses in response to an operating state thereof and for supplying said scan pulses and said sustain pulses to said sustain electrodes.

An electrode drive circuit performs interlaced scanning, ensuring that the phases of the sustaining pulse in odd-numbered lines and even-numbered lines among L1 to L8 between surface discharge electrodes are the reverse of each other. With this, when either odd-numbered lines or even-numbered lines are displayed, the voltages applied between the electrodes of the undisplayed lines are at 0, eliminating the necessity for partitioning walls on the surface discharge electrodes. In surface discharge electrodes, X electrodes are provided on the two sides of a Y electrode and the area between the Y electrode and the X electrode on one side is assigned a display line at an odd-numbered frame, and the area between the Y electrode and the X electrode on the other side is assigned a display line in an even-numbered frame. Alternate areas between the surface discharge electrodes are assigned as blind lines and a discharge light emission in the blind lines is blocked or incident light to the blind lines from the outside is absorbed. Address electrodes are provided for each monochromatic pixel column and selectively connected with the pads above them, performing simultaneous selection of lines.

The present invention relates to a plasma display device which limits a generation of electromagnetic wave. The plasma display device has first and second drive circuits for applying a drive voltage to first and second display electrode pair. Further, a direction of a charge current flowing at said first display electrode pair when said drive voltage is applied by said first drive circuit is opposite on said plasma display panel to a direction of a charge current flowing at said second display electrode pair when said drive voltage is applied by said second drive circuit. According to the present invention, a transitional charge/discharge current, which is generated upon the application of a drive voltage to one of the display electrodes, and a light emission discharge current flow in opposite directions on the panel. Thus, electromagnetic waves that are generated by the inductances of the display electrode pair cancel each other out. In addition, the currents flowing in opposing directions cancel each other out on the common ground wirings which are connected to the ground wirings of the drive circuits, and electromagnetic wave is reduced.

Plasma display device

A plasma display panel and driving method thereof perform addressing at a high speed and a low voltage without deteriorating contrast. Priming electrodes forming priming cells are located outside but adjacent a display area. Glow occurring in the priming cells is intercepted. When priming discharge is induced at a reset step, voltages lower than a discharge start voltage are applied to first (X) and second (Y) electrodes and third (address) electrodes respectively. Despite the voltages being lower than the discharge start voltage, once discharge is induced in the priming cells, discharge starts in adjoining cells. The discharge then spreads successively over all the cells, thus inducing discharge in all the cells. Consequently, wall charge is produced in all the cells.

Plasma display panel having dedicated priming electrodes outside display

A display apparatus permitting high resolution and a large number of gray-scale levels and causing indiscernible flicker has been disclosed. One frame is divided into or composed of j subframes, and light is produced according to a luminance level predetermined subframe by subframe in order to express intermediate gray-scale of a picture. Emphasis is put on the fact that display to be performed during each subframe within one frame can be controlled independently. An interlaced-scanning display is carried out during k subframes associated with low-order weighted bits out of j subframes, and a noninterlaced-scanning display is carried out during the other j-k subframes associated with high-order weighted bits. The ratio of an addressing scan time to a subframe associated with a small weight is large, and the ratio of an addressing scan time to a whole frame is very large. If the addressing scan time can be reduced as mentioned above, a great effect would be exerted. Moreover, the luminance levels to be determined in relation to the subframes during which interlaced-scanning display is carried out are so low that the influence of the reduction on a whole picture is limited.

Display method for intermediate gray scale and display apparatus for

A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source. The level conversion circuit is supplied with power from the first driving power source, and converts an output signal of the first circuit system into an input signal of the second circuit system. The second circuit system drives a signal with level converted by being supplied with power from the second driving power source. Further, in the semiconductor integrated circuit, a bidirectional level conversion circuit and a signal control means are provided, and the first and the second driving power sources are wired in a lattice form in a semiconductor chip.

Level converter for CMOS 3V to from 5V

A constant voltage supplying circuit is disposed between a voltage output terminal of a voltage generation circuit for outputting a voltage having the same polarity as that of a reference voltage, which can be arbitrarily set, and having a greater absolute value than the reference voltage, and a load. This constant voltage supplying circuit includes a first field effect transistor a gate of which is connected to its drain, and to a source of which the reference voltage is supplied, and a second field effect transistor which has the same conductivity type as the first field effect transistor, a gate of which is connected to the drain of the first field effect transistor, a source of which is connected to the voltage output terminal of the voltage generation circuit, and a drain of which is connected to the ground. According to the circuit constitution, the output voltage of the voltage generation circuit can be stabilized to a desired voltage value (the same voltage value as the reference voltage). Even when the constant voltage supplying circuit is fabricated in an integrated circuit, it does not invite the increase of the production process, and thus can limit the increase of the cost of production.

Constant voltage supplying circuit

A synchronizing circuit has a first signal generating unit for dividing a control signal to obtain a first signal having a first frequency, a second signal generating unit for dividing the control signal to obtain a second signal having a second frequency, a third signal generating unit for dividing the control signal to obtain a third signal having a third frequency and synchronized with the second signal, and a synchronizing signal generating unit for generating a synchronizing signal which is adapted to synchronize the first signal with the second and third signals in accordance with a logical operation on the first, second and third signals. With this arrangement, the internal clock signals can be synchronized without using a reset signal. Consequently, neither wiring for supplying the reset signal nor a circuit for generating the reset signal are necessary.

Synchronizing circuit for dividing a frequency of a clock signal

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Kawasaki, Japan

Fumitaka Asami